ReactOS  0.4.14-dev-606-g14ebc0b
compat.h
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1 #pragma once
2 
3 #define __init
4 #define __initdata
5 
6 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
7 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
8 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
9 #define SPRN_LDSTDB 0x3f4 /* */
10 #define SPRN_LR 0x008 /* Link Register */
11 #ifndef SPRN_PIR
12 #define SPRN_PIR 0x3FF /* Processor Identification Register */
13 #endif
14 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
15 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
16 #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
17 #define SPRN_PVR 0x11F /* Processor Version Register */
18 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
19 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
20 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
21 #define SPRN_ASR 0x118 /* Address Space Register */
22 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
23 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
24 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
25 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
26 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
27 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
28 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
29 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
30 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
31 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
32 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
33 #ifndef SPRN_SVR
34 #define SPRN_SVR 0x11E /* System Version Register */
35 #endif
36 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
37 /* these bits were defined in inverted endian sense originally, ugh, confusing */
38 
39 /* Values for PP (assumes Ks=0, Kp=1) */
40 #define PP_RWXX 0 /* Supervisor read/write, User none */
41 #define PP_RWRX 1 /* Supervisor read/write, User read */
42 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
43 #define PP_RXRX 3 /* Supervisor read, User read */
44 
45 /* Block size masks */
46 #define BL_128K 0x000
47 #define BL_256K 0x001
48 #define BL_512K 0x003
49 #define BL_1M 0x007
50 #define BL_2M 0x00F
51 #define BL_4M 0x01F
52 #define BL_8M 0x03F
53 #define BL_16M 0x07F
54 #define BL_32M 0x0FF
55 #define BL_64M 0x1FF
56 #define BL_128M 0x3FF
57 #define BL_256M 0x7FF
58 
59 /* BAT Access Protection */
60 #define BPP_XX 0x00 /* No access */
61 #define BPP_RX 0x01 /* Read only */
62 #define BPP_RW 0x02 /* Read/write */
63 
64 /* Definitions for 40x embedded chips. */
65 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
66 #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */
67 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
68 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
69 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
70 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
71 #define _PAGE_RW 0x040 /* software: Writes permitted */
72 #define _PAGE_DIRTY 0x080 /* software: dirty page */
73 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
74 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
75 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
76 
77 #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
78 #define _PMD_BAD 0x802
79 #define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */
80 #define _PMD_SIZE_4M 0x0c0
81 #define _PMD_SIZE_16M 0x0e0
82 #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
83 
84 #define PVR_VER(pvr)(((pvr) >> 16) & 0xFFFF) /* Version field */
85 
86 #define KERNELBASE 0x80000000
87 
88 typedef unsigned char __u8;
89 typedef unsigned short __u16;
90 typedef unsigned int __u32;
91 
92 typedef struct _pci_reg_property {
93  struct {
94  int a_hi, a_mid, a_lo;
95  } addr;
98 
99 void btext_drawstring(const char *c);
100 void btext_drawhex(unsigned long v);
101 
102 void *ioremap(__u32 phys, __u32 size);
103 void iounmap(void *logical);
104 
105 __u32 GetPVR(void);
unsigned char __u8
Definition: compat.h:88
__u32 GetPVR(void)
void btext_drawhex(unsigned long v)
void btext_drawstring(const char *c)
struct _pci_reg_property::@150 addr
struct _pci_reg_property pci_reg_property
GLsizeiptr size
Definition: glext.h:5919
unsigned short __u16
Definition: compat.h:89
const GLubyte * c
Definition: glext.h:8905
unsigned int __u32
Definition: compat.h:90
void iounmap(void *logical)
const GLdouble * v
Definition: gl.h:2040
void * ioremap(__u32 phys, __u32 size)