ReactOS  0.4.15-dev-1187-g119f102
serial_port.h
Go to the documentation of this file.
1 /*++
2 
3 Copyright (c) 1998-2001 Klaus P. Gerlicher
4 
5 Module Name:
6 
7  serial_port.h
8 
9 Abstract:
10 
11  HEADER for serial.c
12 
13  serial port HW defines
14 
15 Environment:
16 
17  LINUX 2.2.X
18  Kernel mode only
19 
20 Author:
21 
22  Klaus P. Gerlicher
23 
24 Revision History:
25 
26  15-Nov-2000: general cleanup of source files
27 
28 Copyright notice:
29 
30  This file may be distributed under the terms of the GNU Public License.
31 
32 --*/
33 #define COM1 1
34 #define COM2 2
35 #define COM1BASE 0x3F8 /* Base port address for COM1 */
36 #define COM2BASE 0x2F8 /* Base port address for COM2 */
37 
38 // FIX these
39 #define COM3BASE 0x3F8 /* Base port address for COM3 */
40 #define COM4BASE 0x2F8 /* Base port address for COM4 */
41 
42 /*
43  The 8250 UART has 10 registers accessible through 7 port addresses.
44  Here are their addresses relative to COM1BASE and COM2BASE. Note
45  that the baud rate registers, (DLL) and (DLH) are active only when
46  the Divisor-Latch Access-Bit (DLAB) is on. The (DLAB) is bit 7 of
47  the (LCR).
48 
49  o TXR Output data to the serial port.
50  o RXR Input data from the serial port.
51  o LCR Initialize the serial port.
52  o IER Controls interrupt generation.
53  o IIR Identifies interrupts.
54  o MCR Send contorl signals to the modem.
55  o LSR Monitor the status of the serial port.
56  o MSR Receive status of the modem.
57  o DLL Low byte of baud rate divisor.
58  o DHH High byte of baud rate divisor.
59 */
60 #define TXR 0 /* Transmit register (WRITE) */
61 #define RXR 0 /* Receive register (READ) */
62 #define IER 1 /* Interrupt Enable */
63 #define IIR 2 /* Interrupt ID */
64 #define FCR 2 /* FIFO control */
65 #define LCR 3 /* Line control */
66 #define MCR 4 /* Modem control */
67 #define LSR 5 /* Line Status */
68 #define MSR 6 /* Modem Status */
69 #define DLL 0 /* Divisor Latch Low */
70 #define DLH 1 /* Divisor latch High */
71 
72 
73 /*-------------------------------------------------------------------*
74  Bit values held in the Line Control Register (LCR).
75  bit meaning
76  --- -------
77  0-1 00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits.
78  2 Stop bits.
79  3 0=parity off, 1=parity on.
80  4 0=parity odd, 1=parity even.
81  5 Sticky parity.
82  6 Set break.
83  7 Toggle port addresses.
84  *-------------------------------------------------------------------*/
85 #define NO_PARITY 0x00
86 #define EVEN_PARITY 0x18
87 #define ODD_PARITY 0x08
88 
89 
90 
91 /*-------------------------------------------------------------------*
92  Bit values held in the Line Status Register (LSR).
93  bit meaning
94  --- -------
95  0 Data ready.
96  1 Overrun error - Data register overwritten.
97  2 Parity error - bad transmission.
98  3 Framing error - No stop bit was found.
99  4 Break detect - End to transmission requested.
100  5 Transmitter holding register is empty.
101  6 Transmitter shift register is empty.
102  7 Time out - off line.
103  *-------------------------------------------------------------------*/
104 #define RCVRDY 0x01
105 #define OVRERR 0x02
106 #define PRTYERR 0x04
107 #define FRMERR 0x08
108 #define BRKERR 0x10
109 #define XMTRDY 0x20
110 #define XMTRSR 0x40
111 #define TIMEOUT 0x80
112 
113 /*-------------------------------------------------------------------*
114  Bit values held in the Modem Output Control Register (MCR).
115  bit meaning
116  --- -------
117  0 Data Terminal Ready. Computer ready to go.
118  1 Request To Send. Computer wants to send data.
119  2 auxillary output #1.
120  3 auxillary output #2.(Note: This bit must be
121  set to allow the communications card to send
122  interrupts to the system)
123  4 UART ouput looped back as input.
124  5-7 not used.
125  *------------------------------------------------------------------*/
126 #define DTR 0x01
127 #define RTS 0x02
128 
129 
130 /*------------------------------------------------------------------*
131  Bit values held in the Modem Input Status Register (MSR).
132  bit meaning
133  --- -------
134  0 delta Clear To Send.
135  1 delta Data Set Ready.
136  2 delta Ring Indicator.
137  3 delta Data Carrier Detect.
138  4 Clear To Send.
139  5 Data Set Ready.
140  6 Ring Indicator.
141  7 Data Carrier Detect.
142  *------------------------------------------------------------------*/
143 #define CTS 0x10
144 #define DSR 0x20
145 
146 
147 /*------------------------------------------------------------------*
148  Bit values held in the Interrupt Enable Register (IER).
149  bit meaning
150  --- -------
151  0 Interrupt when data received.
152  1 Interrupt when transmitter holding reg. empty.
153  2 Interrupt when data reception error.
154  3 Interrupt when change in modem status register.
155  4-7 Not used.
156  *------------------------------------------------------------------*/
157 #define RX_INT 0x01
158 
159 
160 /*------------------------------------------------------------------*
161  Bit values held in the Interrupt Identification Register (IIR).
162  bit meaning
163  --- -------
164  0 Interrupt pending
165  1-2 Interrupt ID code
166  00=Change in modem status register,
167  01=Transmitter holding register empty,
168  10=Data received,
169  11=reception error, or break encountered.
170  3-7 Not used.
171  *------------------------------------------------------------------*/
172 #define RX_ID 0x04
173 #define RX_MASK 0x07