ReactOS  0.4.15-dev-2534-geba00d1
apic.h
Go to the documentation of this file.
1 /*
2  * PROJECT: ReactOS Kernel
3  * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later)
4  * PURPOSE: Header file for APIC hal
5  * COPYRIGHT: Copyright 2011 Timo Kreuzer <timo.kreuzer@reactos.org>
6  * Copyright 2021 Justin Miller <justinmiller100@gmail.com>
7  */
8 
9 #pragma once
10 
11 #ifdef _M_AMD64
12  #define LOCAL_APIC_BASE 0xFFFFFFFFFFFE0000ULL
13  #define IOAPIC_BASE 0xFFFFFFFFFFFE1000ULL
14  #define APIC_SPURIOUS_VECTOR 0x3f
15  #define IrqlToTpr(Irql) (Irql << 4)
16  #define IrqlToSoftVector(Irql) ((Irql << 4)|0xf)
17  #define TprToIrql(Tpr) ((KIRQL)(Tpr >> 4))
18  #define CLOCK2_LEVEL CLOCK_LEVEL
19 #else
20  #define LOCAL_APIC_BASE 0xFFFE0000
21  #define IOAPIC_BASE 0xFFFE1000
22  #define APIC_SPURIOUS_VECTOR 0x1f
23  #define IrqlToTpr(Irql) (HalpIRQLtoTPR[Irql])
24  #define IrqlToSoftVector(Irql) IrqlToTpr(Irql)
25  #define TprToIrql(Tpr) (HalVectorToIRQL[Tpr >> 4])
26 #endif
27 
28 /* The IMCR is supported by two read/writable or write-only I/O ports,
29  22h and 23h, which receive address and data respectively.
30  To access the IMCR, write a value of 70h to I/O port 22h, which selects the IMCR.
31  Then write the data to I/O port 23h. The power-on default value is zero,
32  which connects the NMI and 8259 INTR lines directly to the BSP.
33  Writing a value of 01h forces the NMI and 8259 INTR signals to pass through the APIC.
34 */
35 #define IMCR_ADDRESS_PORT (PUCHAR)0x0022
36 #define IMCR_DATA_PORT (PUCHAR)0x0023
37 #define IMCR_SELECT 0x70
38 #define IMCR_PIC_DIRECT 0x00
39 #define IMCR_PIC_VIA_APIC 0x01
40 
41 #define ZERO_VECTOR 0x00 // IRQL 00
42 #define APC_VECTOR 0x3D // IRQL 01
43 #define DISPATCH_VECTOR 0x41 // IRQL 02
44 #define APIC_GENERIC_VECTOR 0xC1 // IRQL 27
45 #define APIC_CLOCK_VECTOR 0xD1 // IRQL 28
46 #define APIC_SYNCH_VECTOR 0xD1 // IRQL 28
47 #define APIC_IPI_VECTOR 0xE1 // IRQL 29
48 #define APIC_ERROR_VECTOR 0xE3
49 #define POWERFAIL_VECTOR 0xEF // IRQL 30
50 #define APIC_PROFILE_VECTOR 0xFD // IRQL 31
51 #define APIC_PERF_VECTOR 0xFE
52 #define APIC_NMI_VECTOR 0xFF
53 
54 /* APIC Register Address Map */
55 #define APIC_ID 0x0020 /* Local APIC ID Register (R/W) */
56 #define APIC_VER 0x0030 /* Local APIC Version Register (R) */
57 #define APIC_TPR 0x0080 /* Task Priority Register (R/W) */
58 #define APIC_APR 0x0090 /* Arbitration Priority Register (R) */
59 #define APIC_PPR 0x00A0 /* Processor Priority Register (R) */
60 #define APIC_EOI 0x00B0 /* EOI Register (W) */
61 #define APIC_RRR 0x00C0 /* Remote Read Register () */
62 #define APIC_LDR 0x00D0 /* Logical Destination Register (R/W) */
63 #define APIC_DFR 0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */
64 #define APIC_SIVR 0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
65 #define APIC_ISR 0x0100 /* Interrupt Service Register 0-255 (R) */
66 #define APIC_TMR 0x0180 /* Trigger Mode Register 0-255 (R) */
67 #define APIC_IRR 0x0200 /* Interrupt Request Register 0-255 (r) */
68 #define APIC_ESR 0x0280 /* Error Status Register (R) */
69 #define APIC_ICR0 0x0300 /* Interrupt Command Register 0-31 (R/W) */
70 #define APIC_ICR1 0x0310 /* Interrupt Command Register 32-63 (R/W) */
71 #define APIC_TMRLVTR 0x0320 /* Timer Local Vector Table (R/W) */
72 #define APIC_THRMLVTR 0x0330 /* Thermal Local Vector Table */
73 #define APIC_PCLVTR 0x0340 /* Performance Counter Local Vector Table (R/W) */
74 #define APIC_LINT0 0x0350 /* LINT0 Local Vector Table (R/W) */
75 #define APIC_LINT1 0x0360 /* LINT1 Local Vector Table (R/W) */
76 #define APIC_ERRLVTR 0x0370 /* Error Local Vector Table (R/W) */
77 #define APIC_TICR 0x0380 /* Initial Count Register for Timer (R/W) */
78 #define APIC_TCCR 0x0390 /* Current Count Register for Timer (R) */
79 #define APIC_TDCR 0x03E0 /* Timer Divide Configuration Register (R/W) */
80 #define APIC_EAFR 0x0400 /* extended APIC Feature register (R/W) */
81 #define APIC_EACR 0x0410 /* Extended APIC Control Register (R/W) */
82 #define APIC_SEOI 0x0420 /* Specific End Of Interrupt Register (W) */
83 #define APIC_EXT0LVTR 0x0500 /* Extended Interrupt 0 Local Vector Table */
84 #define APIC_EXT1LVTR 0x0510 /* Extended Interrupt 1 Local Vector Table */
85 #define APIC_EXT2LVTR 0x0520 /* Extended Interrupt 2 Local Vector Table */
86 #define APIC_EXT3LVTR 0x0530 /* Extended Interrupt 3 Local Vector Table */
87 
88 #define MSR_APIC_BASE 0x0000001B
89 #define IOAPIC_PHYS_BASE 0xFEC00000
90 #define APIC_CLOCK_INDEX 8
91 #define ApicLogicalId(Cpu) ((UCHAR)(1<< Cpu))
92 
93 /* Message Type */
94 enum
95 {
104 };
105 
106 /* Trigger Mode */
107 enum
108 {
111 };
112 
113 /* Delivery Mode */
114 enum
115 {
118 };
119 
120 /* Destination Short Hand */
121 enum
122 {
127 };
128 
129 /* Write Constants */
130 enum
131 {
132  APIC_DF_Flat = 0xFFFFFFFF,
133  APIC_DF_Cluster = 0x0FFFFFFF
134 };
135 
136 /* Timer Constants */
137 enum
138 {
147 };
148 
149 #include <pshpack1.h>
151 {
153  struct
154  {
161  };
163 
165 {
167  struct
168  {
173  };
175 
177 {
179  struct
180  {
186  };
188 
190 {
192  struct
193  {
198  };
200 
202 {
204  struct
205  {
208  };
209  struct
210  {
222  };
224 
225 typedef union _LVT_REGISTER
226 {
228  struct
229  {
240  };
241 } LVT_REGISTER;
242 
243 /* IOAPIC offsets */
244 enum
245 {
248 };
249 
250 /* IOAPIC Constants */
251 enum
252 {
253  IOAPIC_ID = 0x00,
254  IOAPIC_VER = 0x01,
255  IOAPIC_ARB = 0x02,
257 };
258 
260 {
262  struct
263  {
266  };
267  struct
268  {
279  };
281 #include <poppack.h>
282 
284 ULONG
286 {
287  return *(volatile ULONG *)(APIC_BASE + Offset);
288 }
289 
291 VOID
293 {
294  *(volatile ULONG *)(APIC_BASE + Offset) = Value;
295 }
296 
297 VOID
298 NTAPI
300 
301 VOID
302 NTAPI
304 
305 VOID
306 NTAPI
308 
#define IN
Definition: typedefs.h:39
UINT32 ReservedMBZ
Definition: apic.h:182
UINT32 ReservedMBZ1
Definition: apic.h:184
union _APIC_EXTENDED_CONTROL_REGISTER APIC_EXTENDED_CONTROL_REGISTER
#define __cdecl
Definition: accygwin.h:79
UINT64 RemoteReadStatus
Definition: apic.h:218
UINT64 DestinationShortHand
Definition: apic.h:219
UINT32 Vector
Definition: apic.h:230
UINT32 DeliveryStatus
Definition: apic.h:233
#define APIC_BASE
Definition: mboot.c:45
VOID __cdecl ApicSpuriousService(VOID)
UINT32 Reserved2MBZ
Definition: apic.h:239
UINT32 Long
Definition: apic.h:227
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
unsigned int UINT32
union _APIC_COMMAND_REGISTER APIC_COMMAND_REGISTER
UINT64 DestinationMode
Definition: apic.h:213
UINT64 MessageType
Definition: apic.h:212
union _APIC_BASE_ADRESS_REGISTER APIC_BASE_ADRESS_REGISTER
PLOADER_PARAMETER_BLOCK KeLoaderBlock
Definition: krnlinit.c:29
UINT32 Reserved1MBZ
Definition: apic.h:234
UINT32 TimerMode
Definition: apic.h:238
UINT32 Mask
Definition: apic.h:237
_Must_inspect_result_ _In_ WDFKEY _In_ PCUNICODE_STRING _Out_opt_ PUSHORT _Inout_opt_ PUNICODE_STRING Value
Definition: wdfregistry.h:406
UINT32 ReservedMBZ
Definition: apic.h:232
UINT32 RemoteIRR
Definition: apic.h:235
VOID NTAPI ApicInitializeTimer(ULONG Cpu)
Definition: apictimer.c:50
UINT32 MessageType
Definition: apic.h:231
union _APIC_SPURIOUS_INERRUPT_REGISTER APIC_SPURIOUS_INERRUPT_REGISTER
union _APIC_VERSION_REGISTER APIC_VERSION_REGISTER
FORCEINLINE ULONG ApicRead(ULONG Offset)
Definition: apic.h:285
VOID NTAPI HalInitializeProfiling(VOID)
Definition: apictimer.c:69
UINT64 Destination
Definition: apic.h:221
UINT32 ExtRegSpacePresent
Definition: apic.h:185
_In_ ULONG _In_ ULONG Offset
Definition: ntddpcm.h:101
union _LVT_REGISTER LVT_REGISTER
union _IOAPIC_REDIRECTION_REGISTER IOAPIC_REDIRECTION_REGISTER
FORCEINLINE VOID ApicWrite(ULONG Offset, ULONG Value)
Definition: apic.h:292
#define FORCEINLINE
Definition: wdftypes.h:67
UINT64 TriggerMode
Definition: apic.h:217
VOID NTAPI HalpInitApicInfo(IN PLOADER_PARAMETER_BLOCK KeLoaderBlock)
UINT64 DeliveryStatus
Definition: apic.h:214
unsigned int ULONG
Definition: retypes.h:1
UINT64 ReservedMBZ
Definition: apic.h:215
unsigned long long UINT64
UINT64 Reserved2MBZ
Definition: apic.h:220
UINT32 TriggerMode
Definition: apic.h:236