ReactOS  0.4.13-dev-961-g238ea69
haldma.h
Go to the documentation of this file.
1 #pragma once
2 
3 /*
4  * DMA Page Register Structure
5  * 080 DMA RESERVED
6  * 081 DMA Page Register (channel 2)
7  * 082 DMA Page Register (channel 3)
8  * 083 DMA Page Register (channel 1)
9  * 084 DMA RESERVED
10  * 085 DMA RESERVED
11  * 086 DMA RESERVED
12  * 087 DMA Page Register (channel 0)
13  * 088 DMA RESERVED
14  * 089 PS/2-DMA Page Register (channel 6)
15  * 08A PS/2-DMA Page Register (channel 7)
16  * 08B PS/2-DMA Page Register (channel 5)
17  * 08C PS/2-DMA RESERVED
18  * 08D PS/2-DMA RESERVED
19  * 08E PS/2-DMA RESERVED
20  * 08F PS/2-DMA Page Register (channel 4)
21  */
22 
23 typedef struct _DMA_PAGE
24 {
38 
39 /*
40  * DMA Channel Mask Register Structure
41  *
42  * MSB LSB
43  * x x x x x x x x
44  * ------------------- - -----
45  * | | | 00 - Select channel 0 mask bit
46  * | | \---- 01 - Select channel 1 mask bit
47  * | | 10 - Select channel 2 mask bit
48  * | | 11 - Select channel 3 mask bit
49  * | |
50  * | \---------- 0 - Clear mask bit
51  * | 1 - Set mask bit
52  * |
53  * \----------------------- xx - Reserved
54  */
55 
56 typedef struct _DMA_CHANNEL_MASK
57 {
62 
63 /*
64  * DMA Mask Register Structure
65  *
66  * MSB LSB
67  * x x x x x x x x
68  * \---/ - - ----- -----
69  * | | | | | 00 - Channel 0 select
70  * | | | | \---- 01 - Channel 1 select
71  * | | | | 10 - Channel 2 select
72  * | | | | 11 - Channel 3 select
73  * | | | |
74  * | | | | 00 - Verify transfer
75  * | | | \------------ 01 - Write transfer
76  * | | | 10 - Read transfer
77  * | | |
78  * | | \-------------------- 0 - Autoinitialized
79  * | | 1 - Non-autoinitialized
80  * | |
81  * | \------------------------ 0 - Address increment select
82  * |
83  * | 00 - Demand mode
84  * \------------------------------ 01 - Single mode
85  * 10 - Block mode
86  * 11 - Cascade mode
87  */
88 
89 typedef union _DMA_MODE
90 {
91  struct
92  {
98  };
100 } DMA_MODE, *PDMA_MODE;
101 
102 /*
103  * DMA Extended Mode Register Structure
104  *
105  * MSB LSB
106  * x x x x x x x x
107  * - - ----- ----- -----
108  * | | | | | 00 - Channel 0 select
109  * | | | | \---- 01 - Channel 1 select
110  * | | | | 10 - Channel 2 select
111  * | | | | 11 - Channel 3 select
112  * | | | |
113  * | | | | 00 - 8-bit I/O, by bytes
114  * | | | \------------ 01 - 16-bit I/O, by words, address shifted
115  * | | | 10 - 32-bit I/O, by bytes
116  * | | | 11 - 16-bit I/O, by bytes
117  * | | |
118  * | | \---------------------- 00 - Compatible
119  * | | 01 - Type A
120  * | | 10 - Type B
121  * | | 11 - Burst
122  * | |
123  * | \---------------------------- 0 - Terminal Count is Output
124  * |
125  * \---------------------------------0 - Disable Stop Register
126  * 1 - Enable Stop Register
127  */
128 
129 typedef union _DMA_EXTENDED_MODE
130 {
131  struct
132  {
138  };
141 
142 /* DMA Extended Mode Register Transfer Sizes */
143 #define B_8BITS 0
144 #define W_16BITS 1
145 #define B_32BITS 2
146 #define B_16BITS 3
147 
148 /* DMA Extended Mode Register Timing */
149 #define COMPATIBLE_TIMING 0
150 #define TYPE_A_TIMING 1
151 #define TYPE_B_TIMING 2
152 #define BURST_TIMING 3
153 
154 /* Channel Stop Registers for each Channel */
155 typedef struct _DMA_CHANNEL_STOP
156 {
162 
163 /* Transfer Types */
164 #define VERIFY_TRANSFER 0x00
165 #define READ_TRANSFER 0x01
166 #define WRITE_TRANSFER 0x02
167 
168 /* Request Modes */
169 #define DEMAND_REQUEST_MODE 0x00
170 #define SINGLE_REQUEST_MODE 0x01
171 #define BLOCK_REQUEST_MODE 0x02
172 #define CASCADE_REQUEST_MODE 0x03
173 
174 #define DMA_SETMASK 4
175 #define DMA_CLEARMASK 0
176 #define DMA_READ 4
177 #define DMA_WRITE 8
178 #define DMA_SINGLE_TRANSFER 0x40
179 #define DMA_AUTO_INIT 0x10
180 
181 typedef struct _DMA1_ADDRESS_COUNT
182 {
186 
187 typedef struct _DMA2_ADDRESS_COUNT
188 {
194 
195 typedef struct _DMA1_CONTROL
196 {
207 
208 typedef struct _DMA2_CONTROL
209 {
228 
229 /* This structure defines the I/O Map of the 82537 controller. */
230 typedef struct _EISA_CONTROL
231 {
232  /* DMA Controller 1 */
234  UCHAR Reserved1[16]; /* 0Fh-1Fh */
235 
236  /* Interrupt Controller 1 (PIC) */
237  UCHAR Pic1Operation; /* 20h */
238  UCHAR Pic1Interrupt; /* 21h */
239  UCHAR Reserved2[30]; /* 22h-3Fh */
240 
241  /* Timer */
242  UCHAR TimerCounter; /* 40h */
244  UCHAR Speaker; /* 42h */
246  UCHAR TimerMisc; /* 44h */
247  UCHAR Reserved3[2]; /* 45-46h */
250  UCHAR Reserved4; /* 49h */
251  UCHAR TimerCounter2; /* 4Ah */
253  UCHAR Reserved5[20]; /* 4Ch-5Fh */
254 
255  /* NMI / Keyboard / RTC */
256  UCHAR Keyboard; /* 60h */
257  UCHAR NmiStatus; /* 61h */
258  UCHAR Reserved6[14]; /* 62h-6Fh */
259  UCHAR NmiEnable; /* 70h */
260  UCHAR Reserved7[15]; /* 71h-7Fh */
261 
262  /* DMA Page Registers Controller 1 */
264  UCHAR Reserved8[16]; /* 90h-9Fh */
265 
266  /* Interrupt Controller 2 (PIC) */
267  UCHAR Pic2Operation; /* 0A0h */
268  UCHAR Pic2Interrupt; /* 0A1h */
269  UCHAR Reserved9[30]; /* 0A2h-0BFh */
270 
271  /* DMA Controller 2 */
272  DMA1_CONTROL DmaController2; /* 0C0h-0CFh */
273 
274  /* System Reserved Ports */
275  UCHAR SystemReserved[816]; /* 0D0h-3FFh */
276 
277  /* Extended DMA Registers, Controller 1 */
278  UCHAR DmaHighByteCount1[8]; /* 400h-407h */
279  UCHAR Reserved10[2]; /* 408h-409h */
280  UCHAR DmaChainMode1; /* 40Ah */
283  UCHAR Reserved11[84]; /* 40Dh-460h */
285  UCHAR NmiCommand; /* 462h */
286  UCHAR Reserved12; /* 463h */
287  UCHAR BusMaster; /* 464h */
288  UCHAR Reserved13[27]; /* 465h-47Fh */
289 
290  /* DMA Page Registers Controller 2 */
291  DMA_PAGE DmaController2Pages; /* 480h-48Fh */
292  UCHAR Reserved14[48]; /* 490h-4BFh */
293 
294  /* Extended DMA Registers, Controller 2 */
295  UCHAR DmaHighByteCount2[16]; /* 4C0h-4CFh */
296 
297  /* Edge/Level Control Registers */
298  UCHAR Pic1EdgeLevel; /* 4D0h */
299  UCHAR Pic2EdgeLevel; /* 4D1h */
300  UCHAR Reserved15[2]; /* 4D2h-4D3h */
301 
302  /* Extended DMA Registers, Controller 2 */
303  UCHAR DmaChainMode2; /* 4D4h */
304  UCHAR Reserved16; /* 4D5h */
306  UCHAR Reserved17[9]; /* 4D7h-4DFh */
307 
308  /* DMA Stop Registers */
309  DMA_CHANNEL_STOP DmaChannelStop[8]; /* 4E0h-4FFh */
311 
313 {
318 
319 typedef struct _ADAPTER_OBJECT {
320  /*
321  * New style DMA object definition. The fact that it is at the beginning
322  * of the ADAPTER_OBJECT structure allows us to easily implement the
323  * fallback implementation of IoGetDmaAdapter.
324  */
326 
327  /*
328  * For normal adapter objects pointer to master adapter that takes care
329  * of channel allocation. For master adapter set to NULL.
330  */
332 
336 
339 
360 
361 typedef struct _GROW_WORK_ITEM {
366 
367 #define MAP_BASE_SW_SG 1
368 
371 
374  IN PVOID Context,
377 
378 ULONG NTAPI
380  PADAPTER_OBJECT AdapterObject);
UCHAR DmaBaseCount
Definition: haldma.h:184
UCHAR Reserved3[2]
Definition: haldma.h:247
UCHAR Reserved4
Definition: haldma.h:250
UCHAR DmaStatus
Definition: haldma.h:211
DMA_CHANNEL_STOP DmaChannelStop[8]
Definition: haldma.h:309
struct _DMA1_ADDRESS_COUNT * PDMA1_ADDRESS_COUNT
#define IN
Definition: typedefs.h:38
UCHAR AdapterNumber
Definition: haldma.h:348
UCHAR NmiCommand
Definition: haldma.h:285
UCHAR Pic2EdgeLevel
Definition: haldma.h:299
BOOLEAN NeedsMapRegisters
Definition: haldma.h:351
UCHAR AutoInitialize
Definition: haldma.h:95
UCHAR Reserved13[27]
Definition: haldma.h:288
UCHAR Reserved17[9]
Definition: haldma.h:306
UCHAR DmaBaseAddress
Definition: haldma.h:183
DMA1_ADDRESS_COUNT DmaAddressCount[4]
Definition: haldma.h:197
UCHAR Pic1Operation
Definition: haldma.h:237
UCHAR ChannelLow
Definition: haldma.h:157
PRTL_BITMAP MapRegisters
Definition: haldma.h:345
UCHAR DmaStatus
Definition: haldma.h:198
BOOLEAN Dma64BitAddresses
Definition: haldma.h:357
_Out_ PULONG NumberOfMapRegisters
Definition: halfuncs.h:209
UCHAR SingleMask
Definition: haldma.h:215
UCHAR TimerOperation2
Definition: haldma.h:252
UCHAR TimerCounter2
Definition: haldma.h:251
ULONG NTAPI HalpDmaGetDmaAlignment(PADAPTER_OBJECT AdapterObject)
Definition: dma.c:918
UCHAR ClearMask
Definition: haldma.h:204
UCHAR Channel6
Definition: haldma.h:32
UCHAR TimerCounter
Definition: haldma.h:242
UCHAR Reserved7
Definition: haldma.h:224
union _DMA_EXTENDED_MODE * PDMA_EXTENDED_MODE
UCHAR Speaker
Definition: haldma.h:244
UCHAR Reserved5[20]
Definition: haldma.h:253
UCHAR Reserved
Definition: haldma.h:60
struct _DMA_CHANNEL_STOP DMA_CHANNEL_STOP
union _DMA_MODE DMA_MODE
UCHAR Mode
Definition: haldma.h:217
UCHAR Reserved12
Definition: haldma.h:286
UCHAR Channel
Definition: haldma.h:58
unsigned char * PUCHAR
Definition: retypes.h:3
struct _ROS_MAP_REGISTER_ENTRY ROS_MAP_REGISTER_ENTRY
UCHAR Reserved5
Definition: haldma.h:220
UCHAR DmaBaseAddress
Definition: haldma.h:189
struct _ADAPTER_OBJECT ADAPTER_OBJECT
Definition: haldma.h:312
DMA2_ADDRESS_COUNT DmaAddressCount[4]
Definition: haldma.h:210
UCHAR DmaHighByteCount1[8]
Definition: haldma.h:278
PVOID VirtualAddress
Definition: haldma.h:314
struct _DMA1_ADDRESS_COUNT DMA1_ADDRESS_COUNT
UCHAR Channel2
Definition: haldma.h:26
LIST_ENTRY AdapterQueue
Definition: haldma.h:343
UCHAR Reserved6
Definition: haldma.h:222
DMA_ADAPTER DmaHeader
Definition: haldma.h:325
UCHAR Byte
Definition: haldma.h:99
UCHAR TimerFailSafeCounter
Definition: haldma.h:249
UCHAR AllMask
Definition: haldma.h:225
BOOLEAN Dma32BitAddresses
Definition: haldma.h:356
UCHAR Channel1
Definition: haldma.h:28
UCHAR Reserved10[2]
Definition: haldma.h:279
PDMA_ADAPTER NTAPI HalpGetDmaAdapter(IN PVOID Context, IN PDEVICE_DESCRIPTION DeviceDescription, OUT PULONG NumberOfMapRegisters)
Definition: dma.c:790
DMA_PAGE DmaController1Pages
Definition: haldma.h:263
WORK_QUEUE_ITEM WorkQueueItem
Definition: haldma.h:362
UCHAR Reserved15[2]
Definition: haldma.h:300
UCHAR Channel5
Definition: haldma.h:34
UCHAR Channel4
Definition: haldma.h:36
UCHAR AddressDecrement
Definition: haldma.h:96
UCHAR SingleMask
Definition: haldma.h:200
PADAPTER_OBJECT AdapterObject
Definition: haldma.h:363
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
Definition: IoEaTest.cpp:117
UCHAR Reserved3
Definition: haldma.h:216
UCHAR Channel0
Definition: haldma.h:30
struct _GROW_WORK_ITEM * PGROW_WORK_ITEM
BOOLEAN MasterDevice
Definition: haldma.h:352
UCHAR SetMask
Definition: haldma.h:59
UCHAR Channel
Definition: haldma.h:93
UCHAR Reserved14[48]
Definition: haldma.h:292
UCHAR TimerOperation
Definition: haldma.h:245
UCHAR MasterClear
Definition: haldma.h:221
UCHAR Reserved4
Definition: haldma.h:218
unsigned char BOOLEAN
UCHAR Reserved6[14]
Definition: haldma.h:258
UCHAR Reserved1
Definition: haldma.h:25
UCHAR DmaRequest
Definition: haldma.h:213
USHORT DmaPortAddress
Definition: haldma.h:349
struct _ROS_MAP_REGISTER_ENTRY * PROS_MAP_REGISTER_ENTRY
UCHAR TimerMemoryRefresh
Definition: haldma.h:243
UCHAR ClearBytePointer
Definition: haldma.h:219
UCHAR Reserved8[16]
Definition: haldma.h:264
UCHAR TimerMisc
Definition: haldma.h:246
UCHAR DmaBufferControl
Definition: haldma.h:282
struct _ADAPTER_OBJECT * MasterAdapter
Definition: haldma.h:331
struct _DMA_PAGE DMA_PAGE
DMA1_CONTROL DmaController2
Definition: haldma.h:272
_Must_inspect_result_ _In_ PDEVICE_DESCRIPTION DeviceDescription
Definition: iofuncs.h:1015
ULONG CommittedMapRegisters
Definition: haldma.h:338
KSPIN_LOCK SpinLock
Definition: haldma.h:344
UCHAR TimerCounterControl
Definition: haldma.h:248
struct _EISA_CONTROL EISA_CONTROL
struct _DMA2_CONTROL DMA2_CONTROL
UCHAR NmiEnable
Definition: haldma.h:259
UCHAR ChannelNumber
Definition: haldma.h:347
BOOLEAN ScatterGather
Definition: haldma.h:354
UCHAR Keyboard
Definition: haldma.h:256
struct _DMA1_CONTROL DMA1_CONTROL
struct _DMA2_ADDRESS_COUNT DMA2_ADDRESS_COUNT
struct _DMA_CHANNEL_MASK * PDMA_CHANNEL_MASK
UCHAR Reserved16
Definition: haldma.h:304
UCHAR Reserved2[3]
Definition: haldma.h:29
struct _EISA_CONTROL * PEISA_CONTROL
UCHAR ClearMask
Definition: haldma.h:223
KDEVICE_QUEUE ChannelWaitQueue
Definition: haldma.h:341
struct _DMA_PAGE * PDMA_PAGE
UCHAR Pic1Interrupt
Definition: haldma.h:238
UCHAR ChannelMid
Definition: haldma.h:158
unsigned char UCHAR
Definition: xmlstorage.h:181
UCHAR DmaRequest
Definition: haldma.h:199
UCHAR TransferType
Definition: haldma.h:94
UCHAR DmaBaseCount
Definition: haldma.h:191
PHYSICAL_ADDRESS PhysicalAddress
Definition: haldma.h:315
UCHAR Pic1EdgeLevel
Definition: haldma.h:298
UCHAR ChannelNumber
Definition: haldma.h:133
UCHAR Reserved3
Definition: haldma.h:31
Definition: typedefs.h:117
UCHAR BusMaster
Definition: haldma.h:287
UCHAR NmiStatus
Definition: haldma.h:257
struct _DMA_CHANNEL_MASK DMA_CHANNEL_MASK
UCHAR Pic2Operation
Definition: haldma.h:267
UCHAR DmaExtendedMode2
Definition: haldma.h:305
PROS_MAP_REGISTER_ENTRY MapRegisterBase
Definition: haldma.h:335
struct _DMA2_CONTROL * PDMA2_CONTROL
UCHAR Reserved1
Definition: haldma.h:212
UCHAR Reserved9[30]
Definition: haldma.h:269
UCHAR Reserved11[84]
Definition: haldma.h:283
UCHAR Reserved7[15]
Definition: haldma.h:260
UCHAR DmaChainMode2
Definition: haldma.h:303
UCHAR RequestMode
Definition: haldma.h:97
UCHAR Pic2Interrupt
Definition: haldma.h:268
PVOID AdapterBaseVa
Definition: haldma.h:334
UCHAR TransferSize
Definition: haldma.h:134
unsigned short USHORT
Definition: pedump.c:61
UCHAR Reserved4[3]
Definition: haldma.h:35
DMA_MODE AdapterMode
Definition: haldma.h:350
UCHAR Reserved
Definition: haldma.h:160
ULONG KSPIN_LOCK
Definition: env_spec_w32.h:72
unsigned int * PULONG
Definition: retypes.h:1
PADAPTER_OBJECT NTAPI HalpDmaAllocateMasterAdapter(VOID)
Definition: dma.c:332
BOOLEAN Width16Bits
Definition: haldma.h:353
DMA1_CONTROL DmaController1
Definition: haldma.h:233
struct _GROW_WORK_ITEM GROW_WORK_ITEM
UCHAR EnableStopRegister
Definition: haldma.h:137
struct _DMA1_CONTROL * PDMA1_CONTROL
struct _DMA_CHANNEL_STOP * PDMA_CHANNEL_STOP
#define OUT
Definition: typedefs.h:39
BOOLEAN IgnoreCount
Definition: haldma.h:355
DMA_PAGE DmaController2Pages
Definition: haldma.h:291
UCHAR AllMask
Definition: haldma.h:205
ULONG NumberOfMapRegisters
Definition: haldma.h:337
unsigned int ULONG
Definition: retypes.h:1
PKDEVICE_QUEUE RegisterWaitQueue
Definition: haldma.h:342
UCHAR DmaHighByteCount2[16]
Definition: haldma.h:295
UCHAR Mode
Definition: haldma.h:201
UCHAR Reserved8
Definition: haldma.h:226
UCHAR Channel7
Definition: haldma.h:33
PWAIT_CONTEXT_BLOCK CurrentWcb
Definition: haldma.h:340
ULONG MapRegistersPerChannel
Definition: haldma.h:333
union _DMA_EXTENDED_MODE DMA_EXTENDED_MODE
ULONG NumberOfMapRegisters
Definition: haldma.h:364
UCHAR Channel3
Definition: haldma.h:27
UCHAR Reserved1[16]
Definition: haldma.h:234
UCHAR Reserved2[30]
Definition: haldma.h:239
UCHAR DmaChainMode1
Definition: haldma.h:280
UCHAR ChannelHigh
Definition: haldma.h:159
UCHAR ClearBytePointer
Definition: haldma.h:202
UCHAR MasterClear
Definition: haldma.h:203
UCHAR SystemReserved[816]
Definition: haldma.h:275
UCHAR ExtendedNmiControl
Definition: haldma.h:284
union _DMA_MODE * PDMA_MODE
struct _DMA2_ADDRESS_COUNT * PDMA2_ADDRESS_COUNT
UCHAR TerminalCountIsOutput
Definition: haldma.h:136
LIST_ENTRY AdapterList
Definition: haldma.h:358
ULONG Counter
Definition: haldma.h:316
UCHAR DmaExtendedMode1
Definition: haldma.h:281
UCHAR Reserved2
Definition: haldma.h:214
PUCHAR PagePort
Definition: haldma.h:346
UCHAR TimingMode
Definition: haldma.h:135