149 #define COMPATIBLE_TIMING 0 150 #define TYPE_A_TIMING 1 151 #define TYPE_B_TIMING 2 152 #define BURST_TIMING 3 164 #define VERIFY_TRANSFER 0x00 165 #define READ_TRANSFER 0x01 166 #define WRITE_TRANSFER 0x02 169 #define DEMAND_REQUEST_MODE 0x00 170 #define SINGLE_REQUEST_MODE 0x01 171 #define BLOCK_REQUEST_MODE 0x02 172 #define CASCADE_REQUEST_MODE 0x03 174 #define DMA_SETMASK 4 175 #define DMA_CLEARMASK 0 178 #define DMA_SINGLE_TRANSFER 0x40 179 #define DMA_AUTO_INIT 0x10 367 #define MAP_BASE_SW_SG 1
DMA_CHANNEL_STOP DmaChannelStop[8]
struct _DMA1_ADDRESS_COUNT * PDMA1_ADDRESS_COUNT
BOOLEAN NeedsMapRegisters
DMA1_ADDRESS_COUNT DmaAddressCount[4]
BOOLEAN Dma64BitAddresses
_Out_ PULONG NumberOfMapRegisters
ULONG NTAPI HalpDmaGetDmaAlignment(PADAPTER_OBJECT AdapterObject)
union _DMA_EXTENDED_MODE * PDMA_EXTENDED_MODE
struct _DMA_CHANNEL_STOP DMA_CHANNEL_STOP
struct _ROS_MAP_REGISTER_ENTRY ROS_MAP_REGISTER_ENTRY
struct _ADAPTER_OBJECT ADAPTER_OBJECT
DMA2_ADDRESS_COUNT DmaAddressCount[4]
UCHAR DmaHighByteCount1[8]
struct _DMA1_ADDRESS_COUNT DMA1_ADDRESS_COUNT
UCHAR TimerFailSafeCounter
BOOLEAN Dma32BitAddresses
PDMA_ADAPTER NTAPI HalpGetDmaAdapter(IN PVOID Context, IN PDEVICE_DESCRIPTION DeviceDescription, OUT PULONG NumberOfMapRegisters)
DMA_PAGE DmaController1Pages
WORK_QUEUE_ITEM WorkQueueItem
PADAPTER_OBJECT AdapterObject
NTSTATUS(* NTAPI)(IN PFILE_FULL_EA_INFORMATION EaBuffer, IN ULONG EaLength, OUT PULONG ErrorOffset)
struct _GROW_WORK_ITEM * PGROW_WORK_ITEM
struct _ROS_MAP_REGISTER_ENTRY * PROS_MAP_REGISTER_ENTRY
struct _ADAPTER_OBJECT * MasterAdapter
struct _DMA_PAGE DMA_PAGE
DMA1_CONTROL DmaController2
_Must_inspect_result_ _In_ PDEVICE_DESCRIPTION DeviceDescription
ULONG CommittedMapRegisters
UCHAR TimerCounterControl
struct _EISA_CONTROL EISA_CONTROL
struct _DMA2_CONTROL DMA2_CONTROL
struct _DMA1_CONTROL DMA1_CONTROL
struct _DMA2_ADDRESS_COUNT DMA2_ADDRESS_COUNT
struct _DMA_CHANNEL_MASK * PDMA_CHANNEL_MASK
struct _EISA_CONTROL * PEISA_CONTROL
KDEVICE_QUEUE ChannelWaitQueue
struct _DMA_PAGE * PDMA_PAGE
PHYSICAL_ADDRESS PhysicalAddress
struct _DMA_CHANNEL_MASK DMA_CHANNEL_MASK
PROS_MAP_REGISTER_ENTRY MapRegisterBase
struct _DMA2_CONTROL * PDMA2_CONTROL
PADAPTER_OBJECT NTAPI HalpDmaAllocateMasterAdapter(VOID)
DMA1_CONTROL DmaController1
struct _GROW_WORK_ITEM GROW_WORK_ITEM
struct _DMA1_CONTROL * PDMA1_CONTROL
struct _DMA_CHANNEL_STOP * PDMA_CHANNEL_STOP
DMA_PAGE DmaController2Pages
ULONG NumberOfMapRegisters
PKDEVICE_QUEUE RegisterWaitQueue
UCHAR DmaHighByteCount2[16]
PWAIT_CONTEXT_BLOCK CurrentWcb
ULONG MapRegistersPerChannel
union _DMA_EXTENDED_MODE DMA_EXTENDED_MODE
ULONG NumberOfMapRegisters
UCHAR SystemReserved[816]
union _DMA_MODE * PDMA_MODE
struct _DMA2_ADDRESS_COUNT * PDMA2_ADDRESS_COUNT
UCHAR TerminalCountIsOutput