ReactOS  0.4.15-dev-1623-g66cf1d2
page.c
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1 /*
2  * COPYRIGHT: GPL, See COPYING in the top level directory
3  * PROJECT: ReactOS kernel
4  * FILE: ntoskrnl/mm/amd64/page.c
5  * PURPOSE: Low level memory managment manipulation
6  *
7  * PROGRAMMER: Timo Kreuzer (timo.kreuzer@reactos.org)
8  * ReactOS Portable Systems Group
9  */
10 
11 /* INCLUDES ***************************************************************/
12 
13 #include <ntoskrnl.h>
14 #define NDEBUG
15 #include <debug.h>
16 #include <mm/ARM3/miarm.h>
17 
18 #undef InterlockedExchangePte
19 #define InterlockedExchangePte(pte1, pte2) \
20  InterlockedExchange64((LONG64*)&pte1->u.Long, pte2.u.Long)
21 
22 #define PAGE_EXECUTE_ANY (PAGE_EXECUTE|PAGE_EXECUTE_READ|PAGE_EXECUTE_READWRITE|PAGE_EXECUTE_WRITECOPY)
23 #define PAGE_WRITE_ANY (PAGE_EXECUTE_READWRITE|PAGE_READWRITE|PAGE_EXECUTE_WRITECOPY|PAGE_WRITECOPY)
24 #define PAGE_WRITECOPY_ANY (PAGE_EXECUTE_WRITECOPY|PAGE_WRITECOPY)
25 
26 extern MMPTE HyperTemplatePte;
27 
28 /* GLOBALS *****************************************************************/
29 
30 const
31 ULONG64
33 {
34  //
35  // These are the base MM_ protection flags
36  //
37  0,
38  PTE_READONLY | PTE_ENABLE_CACHE,
39  PTE_EXECUTE | PTE_ENABLE_CACHE,
40  PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
41  PTE_READWRITE | PTE_ENABLE_CACHE,
42  PTE_WRITECOPY | PTE_ENABLE_CACHE,
43  PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
44  PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
45  //
46  // These OR in the MM_NOCACHE flag
47  //
48  0,
49  PTE_READONLY | PTE_DISABLE_CACHE,
50  PTE_EXECUTE | PTE_DISABLE_CACHE,
51  PTE_EXECUTE_READ | PTE_DISABLE_CACHE,
52  PTE_READWRITE | PTE_DISABLE_CACHE,
53  PTE_WRITECOPY | PTE_DISABLE_CACHE,
54  PTE_EXECUTE_READWRITE | PTE_DISABLE_CACHE,
55  PTE_EXECUTE_WRITECOPY | PTE_DISABLE_CACHE,
56  //
57  // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
58  //
59  0,
60  PTE_READONLY | PTE_ENABLE_CACHE,
61  PTE_EXECUTE | PTE_ENABLE_CACHE,
62  PTE_EXECUTE_READ | PTE_ENABLE_CACHE,
63  PTE_READWRITE | PTE_ENABLE_CACHE,
64  PTE_WRITECOPY | PTE_ENABLE_CACHE,
65  PTE_EXECUTE_READWRITE | PTE_ENABLE_CACHE,
66  PTE_EXECUTE_WRITECOPY | PTE_ENABLE_CACHE,
67  //
68  // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
69  //
70  0,
71  PTE_READONLY | PTE_WRITECOMBINED_CACHE,
72  PTE_EXECUTE | PTE_WRITECOMBINED_CACHE,
73  PTE_EXECUTE_READ | PTE_WRITECOMBINED_CACHE,
74  PTE_READWRITE | PTE_WRITECOMBINED_CACHE,
75  PTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
76  PTE_EXECUTE_READWRITE | PTE_WRITECOMBINED_CACHE,
77  PTE_EXECUTE_WRITECOPY | PTE_WRITECOMBINED_CACHE,
78 };
79 
80 const
82 {
115 };
116 
117 /* PRIVATE FUNCTIONS *******************************************************/
118 
119 BOOLEAN
122 {
123  return ((ULONG64)Address >= HYPER_SPACE &&
125 }
126 
127 VOID
129 {
130  if (MiIsHyperspaceAddress(Pte))
131  {
133  }
134  else
135  {
136  __invlpg(Address);
137  }
138 }
139 
140 static
141 PMMPTE
144  PVOID Address,
145  BOOLEAN Create)
146 {
147  PMMPTE Pte;
148  PMMPDE Pde;
149  PMMPPE Ppe;
150  PMMPXE Pxe;
151 
152  /* Make sure the process is correct */
154  {
156  }
157  else
158  {
160  }
161 
162  Pxe = MiAddressToPxe(Address);
163  Ppe = MiAddressToPpe(Address);
164  Pde = MiAddressToPde(Address);
165  Pte = MiAddressToPte(Address);
166 
167  if (Create)
168  {
169  /* Check the PXE */
170  if (Pxe->u.Long == 0)
171  {
172  /* Make it demand zero */
174  }
175 
176  /* Check the PPE */
177  if (Ppe->u.Long == 0)
178  {
179  /* Make it demand zero */
181  }
182 
183  /* Check the PDE */
184  if (Pde->u.Long == 0)
185  {
186  /* Make it demand zero */
188  }
189  }
190  else
191  {
192  /* Check the PXE */
193  if (!Pxe->u.Hard.Valid)
194  return NULL;
195 
196  /* Check the PPE */
197  if (!Ppe->u.Hard.Valid)
198  return NULL;
199 
200  /* Check the PDE */
201  if (!Pde->u.Hard.Valid)
202  return NULL;
203  }
204 
205  return Pte;
206 }
207 
208 static
209 ULONG64
212  PVOID Address)
213 {
214  PMMPTE Pte;
215  ULONG64 PteValue;
216 
218  PteValue = Pte ? Pte->u.Long : 0;
219 
220  if (MiIsHyperspaceAddress(Pte))
222 
223  return PteValue;
224 }
225 
226 ULONG
227 NTAPI
229 {
230  ULONG Protect;
231 
232  if (!Pte.u.Flush.Valid)
233  {
235  }
236  else if (Pte.u.Flush.NoExecute)
237  {
238  if (Pte.u.Flush.CopyOnWrite)
240  else if (Pte.u.Flush.Write)
242  else
244  }
245  else
246  {
247  if (Pte.u.Flush.CopyOnWrite)
249  else if (Pte.u.Flush.Write)
251  else
253  }
254 
255  if (Pte.u.Flush.CacheDisable)
257 
258  if (Pte.u.Flush.WriteThrough)
260 
261  // PAGE_GUARD ?
262  return Protect;
263 }
264 
265 static
266 VOID
268 {
269  Pte->u.Flush.CopyOnWrite = (Protection & PAGE_WRITECOPY_ANY) ? 1 : 0;
270  Pte->u.Flush.Write = (Protection & PAGE_WRITE_ANY) ? 1 : 0;
271  Pte->u.Flush.CacheDisable = (Protection & PAGE_NOCACHE) ? 1 : 0;
272  Pte->u.Flush.WriteThrough = (Protection & PAGE_WRITETHROUGH) ? 1 : 0;
273 
274  // FIXME: This doesn't work. Why?
275  Pte->u.Flush.NoExecute = (Protection & PAGE_EXECUTE_ANY) ? 0 : 1;
276 }
277 
278 /* FUNCTIONS ***************************************************************/
279 
281 NTAPI
283  PVOID Address)
284 {
285  MMPTE Pte;
287  return Pte.u.Hard.Valid ? Pte.u.Hard.PageFrameNumber : 0;
288 }
289 
290 BOOLEAN
291 NTAPI
293 {
294  MMPTE Pte;
296  return (BOOLEAN)Pte.u.Hard.Valid;
297 }
298 
299 BOOLEAN
300 NTAPI
302 {
303  MMPTE Pte;
305 
306  return (Pte.u.Hard.Valid == 0) &&
307  (Pte.u.Trans.Transition == 0) &&
308  (Pte.u.Hard.PageFrameNumber != 0);
309 }
310 
311 BOOLEAN
312 NTAPI
314 {
315  MMPTE Pte;
317  return !Pte.u.Hard.Valid && Pte.u.Soft.Transition;
318 }
319 
320 VOID
321 NTAPI
324  PVOID Address,
325  SWAPENTRY* SwapEntry)
326 {
327  PMMPTE PointerPte;
328 
330 
331  PointerPte = MiAddressToPte(Address);
332  *SwapEntry = PointerPte->u.Long >> 1;
333 }
334 
335 BOOLEAN
336 NTAPI
338 {
339  MMPTE Pte;
341  return Pte.u.Hard.Valid && Pte.u.Hard.Dirty;
342 }
343 
344 ULONG
345 NTAPI
347 {
348  MMPTE Pte;
349 
351 
352  return MiGetPteProtection(Pte);
353 }
354 
355 VOID
356 NTAPI
358 {
359  PMMPTE Pte;
360  MMPTE NewPte;
361 
363  ASSERT(Pte != NULL);
364 
365  NewPte = *Pte;
366 
367  MiSetPteProtection(&NewPte, flProtect);
368 
369  InterlockedExchangePte(Pte, NewPte);
370 
371  MiFlushTlb(Pte, Address);
372 }
373 
374 VOID
375 NTAPI
377 {
378  PMMPTE Pte;
379 
381  if (!Pte)
382  {
383  KeBugCheckEx(MEMORY_MANAGEMENT, 0x1234, (ULONG64)Address, 0, 0);
384  }
385 
386  /* Ckear the dirty bit */
387  if (InterlockedBitTestAndReset64((PVOID)Pte, 6))
388  {
389  if (!MiIsHyperspaceAddress(Pte))
390  __invlpg(Address);
391  }
392 
393  MiFlushTlb(Pte, Address);
394 }
395 
396 VOID
397 NTAPI
399 {
400  PMMPTE Pte;
401 
403  if (!Pte)
404  {
405  KeBugCheckEx(MEMORY_MANAGEMENT, 0x1234, (ULONG64)Address, 0, 0);
406  }
407 
408  /* Ckear the dirty bit */
409  if (InterlockedBitTestAndSet64((PVOID)Pte, 6))
410  {
411  if (!MiIsHyperspaceAddress(Pte))
412  __invlpg(Address);
413  }
414 
415  MiFlushTlb(Pte, Address);
416 }
417 
418 VOID
419 NTAPI
422  PVOID Address,
423  BOOLEAN* WasDirty,
424  PPFN_NUMBER Page)
425 {
426  PFN_NUMBER Pfn;
427  PMMPTE Pte;
428  MMPTE OldPte;
429 
431 
432  if (Pte)
433  {
434  /* Atomically set the entry to zero and get the old value. */
435  OldPte.u.Long = InterlockedExchange64((LONG64*)&Pte->u.Long, 0);
436 
437  if (OldPte.u.Hard.Valid)
438  {
439  Pfn = OldPte.u.Hard.PageFrameNumber;
440  }
441  else
442  Pfn = 0;
443  }
444  else
445  {
446  OldPte.u.Long = 0;
447  Pfn = 0;
448  }
449 
450  /* Return information to the caller */
451  if (WasDirty)
452  *WasDirty = (BOOLEAN)OldPte.u.Hard.Dirty;
453 
454  if (Page)
455  *Page = Pfn;
456 
457  MiFlushTlb(Pte, Address);
458 }
459 
460 VOID
461 NTAPI
463  SWAPENTRY* SwapEntry)
464 {
465  PMMPTE Pte;
466 
468  if (Pte == NULL)
469  {
470  *SwapEntry = 0;
471  return;
472  }
473 
474  if (Pte->u.Trans.Valid || !Pte->u.Trans.Transition)
475  {
476  DPRINT1("Pte %x (want not 1 and 0x800)\n", Pte);
477  KeBugCheck(MEMORY_MANAGEMENT);
478  }
479 
480  *SwapEntry = Pte->u.Long >> 1;
481  MI_ERASE_PTE(Pte);
482 }
483 
484 NTSTATUS
485 NTAPI
487  PVOID Address,
488  SWAPENTRY SwapEntry)
489 {
490  PMMPTE Pte;
491  MMPTE PteValue;
492 
494  {
495  DPRINT1("No process\n");
496  KeBugCheck(MEMORY_MANAGEMENT);
497  }
498  if (Process != NULL && Address >= MmSystemRangeStart)
499  {
500  DPRINT1("Setting kernel address with process context\n");
501  KeBugCheck(MEMORY_MANAGEMENT);
502  }
503 
504  if (SwapEntry & (1ull << 63))
505  {
506  KeBugCheck(MEMORY_MANAGEMENT);
507  }
508 
509  /* Allocate a PTE */
511  if (Pte == NULL)
512  {
513  return STATUS_UNSUCCESSFUL;
514  }
515 
516  NT_ASSERT(Pte->u.Long == 0);
517  PteValue.u.Long = SwapEntry << 1;
518  MI_WRITE_INVALID_PTE(Pte, PteValue);
519 
520  return STATUS_UNSUCCESSFUL;
521 }
522 
523 
524 NTSTATUS
525 NTAPI
528  PVOID Address,
529  ULONG PageProtection,
530  PPFN_NUMBER Pages,
531  ULONG PageCount)
532 {
533  ULONG i;
534  MMPTE TmplPte, *Pte;
535 
537 
538  /* Check if the range is valid */
539  if ((Process == NULL && Address < MmSystemRangeStart) ||
541  {
542  DPRINT1("Address 0x%p is invalid for process %p\n", Address, Process);
543  ASSERT(FALSE);
544  }
545 
546  TmplPte.u.Long = 0;
547  TmplPte.u.Hard.Valid = 1;
548  MiSetPteProtection(&TmplPte, PageProtection);
549 
550  TmplPte.u.Flush.Owner = (Address < MmHighestUserAddress) ? 1 : 0;
551 
552 //__debugbreak();
553 
554  for (i = 0; i < PageCount; i++)
555  {
556  TmplPte.u.Hard.PageFrameNumber = Pages[i];
557 
559 
560 DPRINT("MmCreateVirtualMappingUnsafe, Address=%p, TmplPte=%p, Pte=%p\n",
561  Address, TmplPte.u.Long, Pte);
562 
563  if (InterlockedExchangePte(Pte, TmplPte))
564  {
566  }
567 
568  if (MiIsHyperspaceAddress(Pte))
570 
572  }
573 
574 
575  return STATUS_SUCCESS;
576 }
577 
578 NTSTATUS
579 NTAPI
581  PVOID Address,
582  ULONG Protect,
583  PPFN_NUMBER Pages,
584  ULONG PageCount)
585 {
586  ULONG i;
587 
589 
590  for (i = 0; i < PageCount; i++)
591  {
592  if (!MmIsPageInUse(Pages[i]))
593  {
594  DPRINT1("Page %x not in use\n", Pages[i]);
595  KeBugCheck(MEMORY_MANAGEMENT);
596  }
597  }
598 
599  return MmCreateVirtualMappingUnsafe(Process, Address, Protect, Pages, PageCount);
600 }
601 
602 BOOLEAN
603 NTAPI
606  OUT PULONG_PTR DirectoryTableBase)
607 {
608  KIRQL OldIrql;
609  PFN_NUMBER TableBasePfn, HyperPfn, HyperPdPfn, HyperPtPfn, WorkingSetPfn;
610  PMMPTE SystemPte;
611  MMPTE TempPte, PdePte;
612  ULONG TableIndex;
613  PMMPTE PageTablePointer;
614 
615  /* Make sure we don't already have a page directory setup */
616  ASSERT(Process->Pcb.DirectoryTableBase[0] == 0);
617  ASSERT(Process->Pcb.DirectoryTableBase[1] == 0);
618  ASSERT(Process->WorkingSetPage == 0);
619 
620  /* Choose a process color */
621  Process->NextPageColor = (USHORT)RtlRandom(&MmProcessColorSeed);
622 
623  /* Setup the hyperspace lock */
624  KeInitializeSpinLock(&Process->HyperSpaceLock);
625 
626  /* Lock PFN database */
628 
629  /* Get a page for the table base and one for hyper space. The PFNs for
630  these pages will be initialized in MmInitializeProcessAddressSpace,
631  when we are already attached to the process. */
637 
638  /* Release PFN lock */
640 
641  /* Zero pages */
642  MiZeroPhysicalPage(TableBasePfn);
643  MiZeroPhysicalPage(HyperPfn);
644  MiZeroPhysicalPage(HyperPdPfn);
645  MiZeroPhysicalPage(HyperPtPfn);
646  MiZeroPhysicalPage(WorkingSetPfn);
647 
648  /* Set the base directory pointers */
649  Process->WorkingSetPage = WorkingSetPfn;
650  DirectoryTableBase[0] = TableBasePfn << PAGE_SHIFT;
651  DirectoryTableBase[1] = HyperPfn << PAGE_SHIFT;
652 
653  /* Get a PTE to map the page directory */
654  SystemPte = MiReserveSystemPtes(1, SystemPteSpace);
655  ASSERT(SystemPte != NULL);
656 
657  /* Get its address */
658  PageTablePointer = MiPteToAddress(SystemPte);
659 
660  /* Build the PTE for the page directory and map it */
661  PdePte = ValidKernelPte;
662  PdePte.u.Hard.PageFrameNumber = TableBasePfn;
663  *SystemPte = PdePte;
664 
666  //MiInitializePageDirectoryForProcess(
667 
668  /* Copy the kernel mappings and zero out the rest */
669  TableIndex = PXE_PER_PAGE / 2;
670  RtlZeroMemory(PageTablePointer, TableIndex * sizeof(MMPTE));
671  RtlCopyMemory(PageTablePointer + TableIndex,
672  MiAddressToPxe(0) + TableIndex,
673  PAGE_SIZE - TableIndex * sizeof(MMPTE));
674 
675  /* Sanity check */
676  ASSERT(MiAddressToPxi(MmHyperSpaceEnd) >= TableIndex);
677 
678  /* Setup a PTE for the page directory mappings */
680 
681  /* Update the self mapping of the PML4 */
682  TableIndex = MiAddressToPxi((PVOID)PXE_SELFMAP);
683  TempPte.u.Hard.PageFrameNumber = TableBasePfn;
684  PageTablePointer[TableIndex] = TempPte;
685 
686  /* Write the PML4 entry for hyperspace */
687  TableIndex = MiAddressToPxi((PVOID)HYPER_SPACE);
688  TempPte.u.Hard.PageFrameNumber = HyperPfn;
689  PageTablePointer[TableIndex] = TempPte;
690 
691  /* Map the hyperspace PDPT to the system PTE */
692  PdePte.u.Hard.PageFrameNumber = HyperPfn;
693  *SystemPte = PdePte;
694  __invlpg(PageTablePointer);
695 
696  /* Write the hyperspace entry for the first PD */
697  TempPte.u.Hard.PageFrameNumber = HyperPdPfn;
698  PageTablePointer[0] = TempPte;
699 
700  /* Map the hyperspace PD to the system PTE */
701  PdePte.u.Hard.PageFrameNumber = HyperPdPfn;
702  *SystemPte = PdePte;
703  __invlpg(PageTablePointer);
704 
705  /* Write the hyperspace entry for the first PT */
706  TempPte.u.Hard.PageFrameNumber = HyperPtPfn;
707  PageTablePointer[0] = TempPte;
708 
709  /* Map the hyperspace PT to the system PTE */
710  PdePte.u.Hard.PageFrameNumber = HyperPtPfn;
711  *SystemPte = PdePte;
712  __invlpg(PageTablePointer);
713 
714  /* Write the hyperspace PTE for the working set list index */
715  TempPte.u.Hard.PageFrameNumber = WorkingSetPfn;
716  TableIndex = MiAddressToPti(MmWorkingSetList);
717  PageTablePointer[TableIndex] = TempPte;
718 
720 
721  /* Release the system PTE */
722  MiReleaseSystemPtes(SystemPte, 1, SystemPteSpace);
723 
724  /* Switch to phase 1 initialization */
725  ASSERT(Process->AddressSpaceInitialized == 0);
726  Process->AddressSpaceInitialized = 1;
727 
728  /* Add the process to the session */
730  return TRUE;
731 }
732 
733 /* EOF */
#define PAGE_WRITETHROUGH
Definition: mm.h:85
ULONG64 Valid
Definition: mmtypes.h:66
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Definition: page.c:462
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FORCEINLINE VOID MI_ERASE_PTE(IN PMMPTE PointerPte)
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#define TRUE
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Definition: bug.c:1427
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Definition: page.c:486
BOOLEAN NTAPI MmIsPageSwapEntry(PEPROCESS Process, PVOID Address)
Definition: page.c:313
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static WCHAR Address[46]
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Definition: page.c:346
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Definition: polytest.cpp:61
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Definition: syspte.c:275
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MMPTE HyperTemplatePte
Definition: hypermap.c:22
FORCEINLINE PMMPTE MiAddressToPxe(PVOID Address)
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int64_t LONG64
Definition: typedefs.h:68
FORCEINLINE VOID KeInvalidateTlbEntry(IN PVOID Address)
Definition: ke.h:201
#define ASSERT(a)
Definition: mode.c:45
if(!(yy_init))
Definition: macro.lex.yy.c:714
MMPTE_TRANSITION Trans
Definition: mmtypes.h:220
const ULONG64 MmProtectToPteMask[32]
Definition: page.c:32
#define MI_GET_NEXT_PROCESS_COLOR(x)
Definition: miarm.h:239
ULONG64 Valid
Definition: mmtypes.h:150
VOID MiFlushTlb(PMMPTE Pte, PVOID Address)
Definition: page.c:128
MMPDE DemandZeroPde
Definition: page.c:114
HARDWARE_PTE_ARMV6 TempPte
Definition: winldr.c:76
MMPTE ValidKernelPte
Definition: page.c:111
ULONG NTAPI MiGetPteProtection(MMPTE Pte)
Definition: page.c:228
#define MmDeleteHyperspaceMapping(x)
Definition: mm.h:1033
#define STATUS_UNSUCCESSFUL
Definition: udferr_usr.h:132
#define HYPER_SPACE_END
Definition: mm.h:15
unsigned __int64 ULONG64
Definition: imports.h:198
_Requires_lock_held_ Interrupt _Releases_lock_ Interrupt _In_ _IRQL_restores_ KIRQL OldIrql
Definition: kefuncs.h:790
FORCEINLINE ULONG MiAddressToPxi(PVOID Address)
Definition: mm.h:193
#define PAGE_SIZE
Definition: env_spec_w32.h:49
const ULONG MmProtectToValue[32]
Definition: page.c:81
VOID NTAPI MmSetPageProtect(PEPROCESS Process, PVOID Address, ULONG flProtect)
Definition: page.c:357
PMMWSL MmWorkingSetList
Definition: procsup.c:21
union _MMPTE::@2319 u
BOOLEAN FORCEINLINE MiIsHyperspaceAddress(PVOID Address)
Definition: page.c:121
ULONG_PTR Long
Definition: mmtypes.h:215
PFN_NUMBER NTAPI MiRemoveAnyPage(IN ULONG Color)
Definition: pfnlist.c:475
#define PAGE_WRITE_ANY
Definition: page.c:23
MMPTE_HARDWARE Hard
Definition: mmtypes.h:217
FORCEINLINE VOID MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte, IN MMPTE InvalidPte)
Definition: miarm.h:975
#define PAGE_WRITECOMBINE
Definition: mmtypes.h:78
static PMMPTE MiGetPteForProcess(PEPROCESS Process, PVOID Address, BOOLEAN Create)
Definition: page.c:142
ULONG64 Valid
Definition: mmtypes.h:98
GLsizei GLenum const GLvoid GLsizei GLenum GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLint GLint GLint GLshort GLshort GLshort GLubyte GLubyte GLubyte GLuint GLuint GLuint GLushort GLushort GLushort GLbyte GLbyte GLbyte GLbyte GLdouble GLdouble GLdouble GLdouble GLfloat GLfloat GLfloat GLfloat GLint GLint GLint GLint GLshort GLshort GLshort GLshort GLubyte GLubyte GLubyte GLubyte GLuint GLuint GLuint GLuint GLushort GLushort GLushort GLushort GLboolean const GLdouble const GLfloat const GLint const GLshort const GLbyte const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLdouble const GLfloat const GLfloat const GLint const GLint const GLshort const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort const GLdouble const GLfloat const GLint const GLshort GLenum GLenum GLenum GLfloat GLenum GLint GLenum GLenum GLenum GLfloat GLenum GLenum GLint GLenum GLfloat GLenum GLint GLint GLushort GLenum GLenum GLfloat GLenum GLenum GLint GLfloat const GLubyte GLenum GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLint GLint GLsizei GLsizei GLint GLenum GLenum const GLvoid GLenum GLenum const GLfloat GLenum GLenum const GLint GLenum GLenum const GLdouble GLenum GLenum const GLfloat GLenum GLenum const GLint GLsizei GLuint GLfloat GLuint GLbitfield GLfloat GLint GLuint GLboolean GLenum GLfloat GLenum GLbitfield GLenum GLfloat GLfloat GLint GLint const GLfloat GLenum GLfloat GLfloat GLint GLint GLfloat GLfloat GLint GLint const GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat GLint GLfloat GLfloat const GLdouble const GLfloat const GLdouble const GLfloat GLint i
Definition: glfuncs.h:248
unsigned short USHORT
Definition: pedump.c:61
ULONG64 Transition
Definition: mmtypes.h:90
ULONG_PTR SWAPENTRY
Definition: mm.h:47
#define FORCEINLINE
Definition: wdftypes.h:67
BOOLEAN NTAPI MmCreateProcessAddressSpace(IN ULONG MinWs, IN PEPROCESS Process, OUT PULONG_PTR DirectoryTableBase)
Definition: page.c:604
MMPTE_SOFTWARE Soft
Definition: mmtypes.h:219
VOID NTAPI MmGetPageFileMapping(PEPROCESS Process, PVOID Address, SWAPENTRY *SwapEntry)
Definition: page.c:322
#define NULL
Definition: types.h:112
PVOID MmHighestUserAddress
Definition: rtlcompat.c:29
#define PAGE_READONLY
Definition: compat.h:138
#define PAGE_WRITECOPY
Definition: nt_native.h:1305
#define DPRINT1
Definition: precomp.h:8
ULONG64 Write
Definition: mmtypes.h:67
_Must_inspect_result_ _In_ PLARGE_INTEGER _In_ PLARGE_INTEGER _In_ ULONG _In_ PFILE_OBJECT _In_ PVOID Process
Definition: fsrtlfuncs.h:219
__INTRIN_INLINE void __invlpg(void *Address)
Definition: intrin_x86.h:1897
VOID NTAPI MiSessionAddProcess(IN PEPROCESS NewProcess)
Definition: session.c:427
#define BOOLEAN
Definition: pedump.c:73
#define OUT
Definition: typedefs.h:40
#define HYPER_SPACE
Definition: mm.h:14
PVOID MmHyperSpaceEnd
Definition: init.c:56
unsigned int ULONG
Definition: retypes.h:1
#define RtlZeroMemory(Destination, Length)
Definition: typedefs.h:262
uint32_t * PULONG_PTR
Definition: typedefs.h:65
ULONG64 PageFrameNumber
Definition: mmtypes.h:171
#define RtlCopyMemory(Destination, Source, Length)
Definition: typedefs.h:263
#define PAGE_EXECUTE_READ
Definition: nt_native.h:1307
#define PAGE_EXECUTE_READWRITE
Definition: nt_native.h:1308
#define STATUS_SUCCESS
Definition: shellext.h:65
static ULONG64 MiGetPteValueForProcess(PEPROCESS Process, PVOID Address)
Definition: page.c:210
FORCEINLINE PVOID MiPteToAddress(PMMPTE PointerPte)
Definition: mm.h:201
FORCEINLINE ULONG MiAddressToPti(PVOID Address)
Definition: mm.h:174
ULONG64 NoExecute
Definition: mmtypes.h:81
#define MmSystemRangeStart
Definition: mm.h:32
NTSTATUS NTAPI MmCreateVirtualMapping(PEPROCESS Process, PVOID Address, ULONG Protect, PPFN_NUMBER Pages, ULONG PageCount)
Definition: page.c:580
VOID NTAPI KeBugCheckEx(_In_ ULONG BugCheckCode, _In_ ULONG_PTR BugCheckParameter1, _In_ ULONG_PTR BugCheckParameter2, _In_ ULONG_PTR BugCheckParameter3, _In_ ULONG_PTR BugCheckParameter4)
Definition: rtlcompat.c:108
ULONG PageFrameNumber
Definition: mmtypes.h:109
#define PAGE_READWRITE
Definition: nt_native.h:1304
#define NT_ASSERT
Definition: rtlfuncs.h:3312