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ns16550.h
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00001 /* 00002 * PROJECT: ReactOS ComPort Library 00003 * LICENSE: BSD - See COPYING.ARM in the top level directory 00004 * FILE: include/reactos/drivers/serial/ns16550.h 00005 * PURPOSE: Header for National Semiconductor 16550 UART 00006 * PROGRAMMERS: ReactOS Portable Systems Group 00007 */ 00008 00009 /* INCLUDES *******************************************************************/ 00010 00011 #pragma once 00012 00013 /* Note: These definitions are the internal definitions used by Microsoft serial 00014 driver (see src/kernel/serial/serial.h in WDK source code). Linux uses its own, as 00015 do most other OS. 00016 */ 00017 00018 #if !defined(SERIAL_REGISTER_STRIDE) 00019 #define SERIAL_REGISTER_STRIDE 1 00020 #endif 00021 00022 #define RECEIVE_BUFFER_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE)) 00023 #define TRANSMIT_HOLDING_REGISTER ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE)) 00024 #define INTERRUPT_ENABLE_REGISTER ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE)) 00025 #define INTERRUPT_IDENT_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE)) 00026 #define FIFO_CONTROL_REGISTER ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE)) 00027 #define LINE_CONTROL_REGISTER ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE)) 00028 #define MODEM_CONTROL_REGISTER ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE)) 00029 #define LINE_STATUS_REGISTER ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE)) 00030 #define MODEM_STATUS_REGISTER ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE)) 00031 #define DIVISOR_LATCH_LSB ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE)) 00032 #define DIVISOR_LATCH_MSB ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE)) 00033 #define SERIAL_REGISTER_SPAN ((ULONG)(7*SERIAL_REGISTER_STRIDE)) 00034 #define SERIAL_STATUS_LENGTH ((ULONG)(1*SERIAL_REGISTER_STRIDE)) 00035 00036 #define SERIAL_DATA_LENGTH_5 0x00 00037 #define SERIAL_DATA_LENGTH_6 0x01 00038 #define SERIAL_DATA_LENGTH_7 0x02 00039 #define SERIAL_DATA_LENGTH_8 0x03 00040 00041 #define SERIAL_IER_RDA 0x01 00042 #define SERIAL_IER_THR 0x02 00043 #define SERIAL_IER_RLS 0x04 00044 #define SERIAL_IER_MS 0x08 00045 00046 #define SERIAL_IIR_RLS 0x06 00047 #define SERIAL_IIR_RDA 0x04 00048 #define SERIAL_IIR_CTI 0x0c 00049 #define SERIAL_IIR_THR 0x02 00050 #define SERIAL_IIR_MS 0x00 00051 #define SERIAL_IIR_FIFOS_ENABLED 0xc0 00052 #define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01 00053 #define SERIAL_IIR_MUST_BE_ZERO 0x30 00054 00055 #define SERIAL_FCR_ENABLE ((UCHAR)0x01) 00056 #define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02) 00057 #define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04) 00058 00059 #define SERIAL_1_BYTE_HIGH_WATER ((UCHAR)0x00) 00060 #define SERIAL_4_BYTE_HIGH_WATER ((UCHAR)0x40) 00061 #define SERIAL_8_BYTE_HIGH_WATER ((UCHAR)0x80) 00062 #define SERIAL_14_BYTE_HIGH_WATER ((UCHAR)0xc0) 00063 00064 #define SERIAL_LCR_DLAB 0x80 00065 #define SERIAL_LCR_BREAK 0x40 00066 00067 #define SERIAL_5_DATA ((UCHAR)0x00) 00068 #define SERIAL_6_DATA ((UCHAR)0x01) 00069 #define SERIAL_7_DATA ((UCHAR)0x02) 00070 #define SERIAL_8_DATA ((UCHAR)0x03) 00071 #define SERIAL_DATA_MASK ((UCHAR)0x03) 00072 00073 #define SERIAL_1_STOP ((UCHAR)0x00) 00074 #define SERIAL_1_5_STOP ((UCHAR)0x04) // Only valid for 5 data bits 00075 #define SERIAL_2_STOP ((UCHAR)0x04) // Not valid for 5 data bits 00076 #define SERIAL_STOP_MASK ((UCHAR)0x04) 00077 00078 #define SERIAL_NONE_PARITY ((UCHAR)0x00) 00079 #define SERIAL_ODD_PARITY ((UCHAR)0x08) 00080 #define SERIAL_EVEN_PARITY ((UCHAR)0x18) 00081 #define SERIAL_MARK_PARITY ((UCHAR)0x28) 00082 #define SERIAL_SPACE_PARITY ((UCHAR)0x38) 00083 #define SERIAL_PARITY_MASK ((UCHAR)0x38) 00084 00085 #define SERIAL_MCR_DTR 0x01 00086 #define SERIAL_MCR_RTS 0x02 00087 #define SERIAL_MCR_OUT1 0x04 00088 #define SERIAL_MCR_OUT2 0x08 00089 #define SERIAL_MCR_LOOP 0x10 00090 #define SERIAL_MCR_TL16C550CAFE 0x20 00091 00092 #define SERIAL_LSR_DR 0x01 00093 #define SERIAL_LSR_OE 0x02 00094 #define SERIAL_LSR_PE 0x04 00095 #define SERIAL_LSR_FE 0x08 00096 #define SERIAL_LSR_BI 0x10 00097 #define SERIAL_LSR_THRE 0x20 00098 #define SERIAL_LSR_TEMT 0x40 00099 #define SERIAL_LSR_FIFOERR 0x80 00100 00101 #define SERIAL_MSR_DCTS 0x01 00102 #define SERIAL_MSR_DDSR 0x02 00103 #define SERIAL_MSR_TERI 0x04 00104 #define SERIAL_MSR_DDCD 0x08 00105 #define SERIAL_MSR_CTS 0x10 00106 #define SERIAL_MSR_DSR 0x20 00107 #define SERIAL_MSR_RI 0x40 00108 #define SERIAL_MSR_DCD 0x80
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