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00001 /* 00002 * miniport.h 00003 * 00004 * Type definitions for miniport drivers 00005 * 00006 * This file is part of the w32api package. 00007 * 00008 * Contributors: 00009 * Created by Casper S. Hornstrup <chorns@users.sourceforge.net> 00010 * 00011 * THIS SOFTWARE IS NOT COPYRIGHTED 00012 * 00013 * This source code is offered for use in the public domain. You may 00014 * use, modify or distribute it freely. 00015 * 00016 * This code is distributed in the hope that it will be useful but 00017 * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY 00018 * DISCLAIMED. This includes but is not limited to warranties of 00019 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00020 * 00021 */ 00022 00023 #ifndef _MINIPORT_ 00024 #define _MINIPORT_ 00025 00026 #ifdef __cplusplus 00027 extern "C" { 00028 #endif 00029 00030 #define EMULATOR_READ_ACCESS 0x01 00031 #define EMULATOR_WRITE_ACCESS 0x02 00032 00033 typedef enum _EMULATOR_PORT_ACCESS_TYPE { 00034 Uchar, 00035 Ushort, 00036 Ulong 00037 } EMULATOR_PORT_ACCESS_TYPE, *PEMULATOR_PORT_ACCESS_TYPE; 00038 00039 00040 typedef struct _EMULATOR_ACCESS_ENTRY { 00041 ULONG BasePort; 00042 ULONG NumConsecutivePorts; 00043 EMULATOR_PORT_ACCESS_TYPE AccessType; 00044 UCHAR AccessMode; 00045 UCHAR StringSupport; 00046 PVOID Routine; 00047 } EMULATOR_ACCESS_ENTRY, *PEMULATOR_ACCESS_ENTRY; 00048 00049 typedef VOID 00050 (NTAPI *PBANKED_SECTION_ROUTINE)( 00051 IN ULONG ReadBank, 00052 IN ULONG WriteBank, 00053 IN PVOID Context); 00054 00055 #ifndef __BROKEN__ 00056 00057 typedef enum _INTERFACE_TYPE { 00058 InterfaceTypeUndefined = -1, 00059 Internal, 00060 Isa, 00061 Eisa, 00062 MicroChannel, 00063 TurboChannel, 00064 PCIBus, 00065 VMEBus, 00066 NuBus, 00067 PCMCIABus, 00068 CBus, 00069 MPIBus, 00070 MPSABus, 00071 ProcessorInternal, 00072 InternalPowerBus, 00073 PNPISABus, 00074 PNPBus, 00075 Vmcs, 00076 MaximumInterfaceType 00077 } INTERFACE_TYPE, *PINTERFACE_TYPE; 00078 00079 typedef enum _KINTERRUPT_MODE { 00080 LevelSensitive, 00081 Latched 00082 } KINTERRUPT_MODE; 00083 00084 typedef VOID (*PINTERFACE_REFERENCE)(PVOID Context); 00085 typedef VOID (*PINTERFACE_DEREFERENCE)(PVOID Context); 00086 00087 typedef enum _BUS_DATA_TYPE { 00088 ConfigurationSpaceUndefined = -1, 00089 Cmos, 00090 EisaConfiguration, 00091 Pos, 00092 CbusConfiguration, 00093 PCIConfiguration, 00094 VMEConfiguration, 00095 NuBusConfiguration, 00096 PCMCIAConfiguration, 00097 MPIConfiguration, 00098 MPSAConfiguration, 00099 PNPISAConfiguration, 00100 SgiInternalConfiguration, 00101 MaximumBusDataType 00102 } BUS_DATA_TYPE, *PBUS_DATA_TYPE; 00103 00104 typedef enum _DMA_WIDTH { 00105 Width8Bits, 00106 Width16Bits, 00107 Width32Bits, 00108 MaximumDmaWidth 00109 } DMA_WIDTH, *PDMA_WIDTH; 00110 00111 typedef enum _DMA_SPEED { 00112 Compatible, 00113 TypeA, 00114 TypeB, 00115 TypeC, 00116 TypeF, 00117 MaximumDmaSpeed 00118 } DMA_SPEED, *PDMA_SPEED; 00119 00120 typedef struct _INTERFACE { 00121 USHORT Size; 00122 USHORT Version; 00123 PVOID Context; 00124 PINTERFACE_REFERENCE InterfaceReference; 00125 PINTERFACE_DEREFERENCE InterfaceDereference; 00126 } INTERFACE, *PINTERFACE; 00127 00128 typedef enum _IRQ_DEVICE_POLICY { 00129 IrqPolicyMachineDefault = 0, 00130 IrqPolicyAllCloseProcessors, 00131 IrqPolicyOneCloseProcessor, 00132 IrqPolicyAllProcessorsInMachine, 00133 IrqPolicySpecifiedProcessors, 00134 IrqPolicySpreadMessagesAcrossAllProcessors 00135 } IRQ_DEVICE_POLICY, *PIRQ_DEVICE_POLICY; 00136 00137 typedef enum _IRQ_PRIORITY { 00138 IrqPriorityUndefined = 0, 00139 IrqPriorityLow, 00140 IrqPriorityNormal, 00141 IrqPriorityHigh 00142 } IRQ_PRIORITY, *PIRQ_PRIORITY; 00143 00144 typedef struct _IO_RESOURCE_DESCRIPTOR { 00145 UCHAR Option; 00146 UCHAR Type; // use CM_RESOURCE_TYPE 00147 UCHAR ShareDisposition; // use CM_SHARE_DISPOSITION 00148 UCHAR Spare1; 00149 USHORT Flags; // use CM resource flag defines 00150 USHORT Spare2; // align 00151 union { 00152 struct { 00153 ULONG Length; 00154 ULONG Alignment; 00155 PHYSICAL_ADDRESS MinimumAddress; 00156 PHYSICAL_ADDRESS MaximumAddress; 00157 } Port; 00158 struct { 00159 ULONG Length; 00160 ULONG Alignment; 00161 PHYSICAL_ADDRESS MinimumAddress; 00162 PHYSICAL_ADDRESS MaximumAddress; 00163 } Memory; 00164 struct { 00165 ULONG MinimumVector; 00166 ULONG MaximumVector; 00167 IRQ_DEVICE_POLICY AffinityPolicy; 00168 IRQ_PRIORITY PriorityPolicy; 00169 KAFFINITY TargetedProcessors; 00170 } Interrupt; 00171 struct { 00172 ULONG MinimumChannel; 00173 ULONG MaximumChannel; 00174 } Dma; 00175 struct { 00176 ULONG Length; 00177 ULONG Alignment; 00178 PHYSICAL_ADDRESS MinimumAddress; 00179 PHYSICAL_ADDRESS MaximumAddress; 00180 } Generic; 00181 struct { 00182 ULONG Data[3]; 00183 } DevicePrivate; 00184 // 00185 // Bus Number information. 00186 // 00187 struct { 00188 ULONG Length; 00189 ULONG MinBusNumber; 00190 ULONG MaxBusNumber; 00191 ULONG Reserved; 00192 } BusNumber; 00193 struct { 00194 ULONG Priority; // use LCPRI_Xxx values in cfg.h 00195 ULONG Reserved1; 00196 ULONG Reserved2; 00197 } ConfigData; 00198 // 00199 // The following structures provide descriptions 00200 // for memory resource requirement greater than MAXULONG 00201 // 00202 struct { 00203 ULONG Length40; 00204 ULONG Alignment40; 00205 PHYSICAL_ADDRESS MinimumAddress; 00206 PHYSICAL_ADDRESS MaximumAddress; 00207 } Memory40; 00208 struct { 00209 ULONG Length48; 00210 ULONG Alignment48; 00211 PHYSICAL_ADDRESS MinimumAddress; 00212 PHYSICAL_ADDRESS MaximumAddress; 00213 } Memory48; 00214 struct { 00215 ULONG Length64; 00216 ULONG Alignment64; 00217 PHYSICAL_ADDRESS MinimumAddress; 00218 PHYSICAL_ADDRESS MaximumAddress; 00219 } Memory64; 00220 } u; 00221 } IO_RESOURCE_DESCRIPTOR, *PIO_RESOURCE_DESCRIPTOR; 00222 00223 #include <guiddef.h> 00224 #endif /* ! __BROKEN__ */ 00225 00226 #ifdef __cplusplus 00227 } 00228 #endif 00229 00230 #endif /* __MINIPORT_H */ Generated on Sun May 27 2012 04:28:05 for ReactOS by
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