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ide.h
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00001 /*++ 00002 00003 Copyright (C) Microsoft Corporation, 1999 - 1999 00004 00005 Module Name: 00006 00007 ide.h 00008 00009 Abstract: 00010 00011 These are the structures and defines that are used in the 00012 PCI IDE mini drivers. 00013 00014 Revision History: 00015 00016 --*/ 00017 00018 00019 #if !defined (___ide_h___) 00020 #define ___ide_h___ 00021 00022 #include "ideuser.h" 00023 00024 #define MAX_IDE_DEVICE 2 00025 #define MAX_IDE_LINE 2 00026 #define MAX_IDE_CHANNEL 2 00027 00028 // 00029 // Some miniports need this structure. 00030 // IdentifyData is passed to the miniport in 00031 // the XfermodeSelect structure 00032 // 00033 00034 // 00035 // IDENTIFY data 00036 // 00037 00038 #pragma pack (1) 00039 typedef struct _IDENTIFY_DATA { 00040 USHORT GeneralConfiguration; // 00 00 00041 USHORT NumCylinders; // 02 1 00042 USHORT Reserved1; // 04 2 00043 USHORT NumHeads; // 06 3 00044 USHORT UnformattedBytesPerTrack; // 08 4 00045 USHORT UnformattedBytesPerSector; // 0A 5 00046 USHORT NumSectorsPerTrack; // 0C 6 00047 USHORT VendorUnique1[3]; // 0E 7-9 00048 UCHAR SerialNumber[20]; // 14 10-19 00049 USHORT BufferType; // 28 20 00050 USHORT BufferSectorSize; // 2A 21 00051 USHORT NumberOfEccBytes; // 2C 22 00052 UCHAR FirmwareRevision[8]; // 2E 23-26 00053 UCHAR ModelNumber[40]; // 36 27-46 00054 UCHAR MaximumBlockTransfer; // 5E 47 00055 UCHAR VendorUnique2; // 5F 00056 USHORT DoubleWordIo; // 60 48 00057 USHORT Capabilities; // 62 49 00058 USHORT Reserved2; // 64 50 00059 UCHAR VendorUnique3; // 66 51 00060 UCHAR PioCycleTimingMode; // 67 00061 UCHAR VendorUnique4; // 68 52 00062 UCHAR DmaCycleTimingMode; // 69 00063 USHORT TranslationFieldsValid:3; // 6A 53 00064 USHORT Reserved3:13; 00065 USHORT NumberOfCurrentCylinders; // 6C 54 00066 USHORT NumberOfCurrentHeads; // 6E 55 00067 USHORT CurrentSectorsPerTrack; // 70 56 00068 ULONG CurrentSectorCapacity; // 72 57-58 00069 USHORT CurrentMultiSectorSetting; // 59 00070 ULONG UserAddressableSectors; // 60-61 00071 USHORT SingleWordDMASupport : 8; // 62 00072 USHORT SingleWordDMAActive : 8; 00073 USHORT MultiWordDMASupport : 8; // 63 00074 USHORT MultiWordDMAActive : 8; 00075 USHORT AdvancedPIOModes : 8; // 64 00076 USHORT Reserved4 : 8; 00077 USHORT MinimumMWXferCycleTime; // 65 00078 USHORT RecommendedMWXferCycleTime; // 66 00079 USHORT MinimumPIOCycleTime; // 67 00080 USHORT MinimumPIOCycleTimeIORDY; // 68 00081 USHORT Reserved5[11]; // 69-79 00082 USHORT MajorRevision; // 80 00083 USHORT MinorRevision; // 81 00084 USHORT Reserved6; // 82 00085 USHORT CommandSetSupport; // 83 00086 USHORT Reserved6a[2]; // 84-85 00087 USHORT CommandSetActive; // 86 00088 USHORT Reserved6b; // 87 00089 USHORT UltraDMASupport : 8; // 88 00090 USHORT UltraDMAActive : 8; // 00091 USHORT Reserved7[11]; // 89-99 00092 ULONG Max48BitLBA[2]; // 100-103 00093 USHORT Reserved7a[22]; // 104-125 00094 USHORT LastLun:3; // 126 00095 USHORT Reserved8:13; 00096 USHORT MediaStatusNotification:2; // 127 00097 USHORT Reserved9:6; 00098 USHORT DeviceWriteProtect:1; 00099 USHORT Reserved10:7; 00100 USHORT Reserved11[128]; // 128-255 00101 } IDENTIFY_DATA, *PIDENTIFY_DATA; 00102 00103 // 00104 // Identify data without the Reserved4. 00105 // 00106 00107 //typedef struct _IDENTIFY_DATA2 { 00108 // USHORT GeneralConfiguration; // 00 00 00109 // USHORT NumCylinders; // 02 1 00110 // USHORT Reserved1; // 04 2 00111 // USHORT NumHeads; // 06 3 00112 // USHORT UnformattedBytesPerTrack; // 08 4 00113 // USHORT UnformattedBytesPerSector; // 0A 5 00114 // USHORT NumSectorsPerTrack; // 0C 6 00115 // USHORT VendorUnique1[3]; // 0E 7-9 00116 // UCHAR SerialNumber[20]; // 14 10-19 00117 // USHORT BufferType; // 28 20 00118 // USHORT BufferSectorSize; // 2A 21 00119 // USHORT NumberOfEccBytes; // 2C 22 00120 // UCHAR FirmwareRevision[8]; // 2E 23-26 00121 // UCHAR ModelNumber[40]; // 36 27-46 00122 // UCHAR MaximumBlockTransfer; // 5E 47 00123 // UCHAR VendorUnique2; // 5F 00124 // USHORT DoubleWordIo; // 60 48 00125 // USHORT Capabilities; // 62 49 00126 // USHORT Reserved2; // 64 50 00127 // UCHAR VendorUnique3; // 66 51 00128 // UCHAR PioCycleTimingMode; // 67 00129 // UCHAR VendorUnique4; // 68 52 00130 // UCHAR DmaCycleTimingMode; // 69 00131 // USHORT TranslationFieldsValid:3; // 6A 53 00132 // USHORT Reserved3:13; 00133 // USHORT NumberOfCurrentCylinders; // 6C 54 00134 // USHORT NumberOfCurrentHeads; // 6E 55 00135 // USHORT CurrentSectorsPerTrack; // 70 56 00136 // ULONG CurrentSectorCapacity; // 72 57-58 00137 // USHORT CurrentMultiSectorSetting; // 59 00138 // ULONG UserAddressableSectors; // 60-61 00139 // USHORT SingleWordDMASupport : 8; // 62 00140 // USHORT SingleWordDMAActive : 8; 00141 // USHORT MultiWordDMASupport : 8; // 63 00142 // USHORT MultiWordDMAActive : 8; 00143 // USHORT AdvancedPIOModes : 8; // 64 00144 // USHORT Reserved4 : 8; 00145 // USHORT MinimumMWXferCycleTime; // 65 00146 // USHORT RecommendedMWXferCycleTime; // 66 00147 // USHORT MinimumPIOCycleTime; // 67 00148 // USHORT MinimumPIOCycleTimeIORDY; // 68 00149 // USHORT Reserved5[11]; // 69-79 00150 // USHORT MajorRevision; // 80 00151 // USHORT MinorRevision; // 81 00152 // USHORT Reserved6[6]; // 82-87 00153 // USHORT UltraDMASupport : 8; // 88 00154 // USHORT UltraDMAActive : 8; // 00155 // USHORT Reserved7[37]; // 89-125 00156 // USHORT LastLun:3; // 126 00157 // USHORT Reserved8:13; 00158 // USHORT MediaStatusNotification:2; // 127 00159 // USHORT Reserved9:6; 00160 // USHORT DeviceWriteProtect:1; 00161 // USHORT Reserved10:7; 00162 //} IDENTIFY_DATA2, *PIDENTIFY_DATA2; 00163 #pragma pack () 00164 00165 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA) 00166 00167 00168 // 00169 // The structure is passed to pci ide mini driver 00170 // TransferModeSelect callback for selecting 00171 // proper transfer mode the the devices connected 00172 // to the given IDE channel 00173 // 00174 typedef struct _PCIIDE_TRANSFER_MODE_SELECT { 00175 00176 // 00177 // Input Parameters 00178 // 00179 00180 // 00181 // IDE Channel Number. 0 or 1 00182 // 00183 ULONG Channel; 00184 00185 // 00186 // Indicate whether devices are present 00187 // 00188 BOOLEAN DevicePresent[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00189 00190 // 00191 // Indicate whether devices are ATA harddisk 00192 // 00193 BOOLEAN FixedDisk[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00194 00195 // 00196 // Indicate whether devices support IO Ready Line 00197 // 00198 BOOLEAN IoReadySupported[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00199 00200 // 00201 // Indicate the data transfer modes devices support 00202 // 00203 ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00204 00205 // 00206 // Indicate devices' best timings for PIO, single word DMA, 00207 // multiword DMA, and Ultra DMA modes 00208 // 00209 ULONG BestPioCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00210 ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00211 ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00212 ULONG BestUDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00213 00214 // 00215 // Indicate devices' current data transfer modes 00216 // 00217 ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00218 00219 // 00220 // The user's choice. This will allow pciidex to 00221 // default to a transfer mode indicated by the mini driver 00222 // 00223 ULONG UserChoiceTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00224 00225 // 00226 // This enables UDMA66 on the intel chipsets 00227 // 00228 ULONG EnableUDMA66; 00229 00230 // 00231 //Some miniports need this 00232 // The miniport will save this data in their deviceExtension 00233 // 00234 IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE]; 00235 00236 00237 // 00238 // Output Parameters 00239 // 00240 00241 // 00242 // Indicate devices' data transfer modes chosen by 00243 // the pcii ide mini drive 00244 // 00245 ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE * MAX_IDE_LINE]; 00246 00247 // 00248 // Transfermode timings 00249 // 00250 PULONG TransferModeTimingTable; 00251 ULONG TransferModeTableLength; 00252 00253 } PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT; 00254 00255 // 00256 // possible ide channel state 00257 // 00258 00259 typedef enum { 00260 ChannelDisabled = 0, 00261 ChannelEnabled, 00262 ChannelStateUnknown 00263 } IDE_CHANNEL_STATE; 00264 00265 00266 // 00267 // Prototype for different PCI IDE mini driver 00268 // callbacks 00269 // 00270 typedef IDE_CHANNEL_STATE 00271 (*PCIIDE_CHANNEL_ENABLED) ( 00272 IN PVOID DeviceExtension, 00273 IN ULONG Channel 00274 ); 00275 00276 typedef BOOLEAN 00277 (*PCIIDE_SYNC_ACCESS_REQUIRED) ( 00278 IN PVOID DeviceExtension 00279 ); 00280 00281 typedef NTSTATUS 00282 (*PCIIDE_TRANSFER_MODE_SELECT_FUNC) ( 00283 IN PVOID DeviceExtension, 00284 IN OUT PPCIIDE_TRANSFER_MODE_SELECT TransferModeSelect 00285 ); 00286 00287 typedef ULONG 00288 (*PCIIDE_USEDMA_FUNC)( 00289 IN PVOID deviceExtension, 00290 IN PVOID cdbCmd, 00291 IN UCHAR targetID 00292 ); 00293 00294 typedef NTSTATUS 00295 (*PCIIDE_UDMA_MODES_SUPPORTED) ( 00296 IDENTIFY_DATA IdentifyData, 00297 PULONG BestXferMode, 00298 PULONG CurrentMode 00299 ); 00300 // 00301 // This structure is for the PCI IDE mini driver to 00302 // return its properties 00303 // 00304 typedef struct _IDE_CONTROLLER_PROPERTIES { 00305 00306 // 00307 // sizeof (IDE_CONTROLLER_PROPERTIES) 00308 // 00309 ULONG Size; 00310 00311 // 00312 // Indicate the amount of memory PCI IDE mini driver 00313 // needs for its private data 00314 // 00315 ULONG ExtensionSize; 00316 00317 // 00318 // Indicate all the data transfer modes the PCI IDE 00319 // controller supports 00320 // 00321 ULONG SupportedTransferMode[MAX_IDE_CHANNEL][MAX_IDE_DEVICE]; 00322 00323 // 00324 // callback to query whether a IDE channel is enabled 00325 // 00326 PCIIDE_CHANNEL_ENABLED PciIdeChannelEnabled; 00327 00328 // 00329 // callback to query whether both IDE channels requires 00330 // synchronized access. (one channel at a time) 00331 // 00332 PCIIDE_SYNC_ACCESS_REQUIRED PciIdeSyncAccessRequired; 00333 00334 // 00335 // callback to select proper transfer modes for the 00336 // given devices 00337 // 00338 PCIIDE_TRANSFER_MODE_SELECT_FUNC PciIdeTransferModeSelect; 00339 00340 // 00341 // at the end of a ATA data transfer, ignores busmaster 00342 // status active bit. Normally, it should be FALSE 00343 // 00344 BOOLEAN IgnoreActiveBitForAtaDevice; 00345 00346 // 00347 // always clear the busmaster interrupt on every interrupt 00348 // generated by the device. Normnally, it should be FALSE 00349 // 00350 BOOLEAN AlwaysClearBusMasterInterrupt; 00351 00352 // 00353 // callback to determine whether DMA should be used or not 00354 // called for every IO 00355 // 00356 PCIIDE_USEDMA_FUNC PciIdeUseDma; 00357 00358 00359 // 00360 // if the miniport needs a different alignment 00361 // 00362 ULONG AlignmentRequirement; 00363 00364 ULONG DefaultPIO; 00365 00366 // 00367 // retrieves the supported udma modes from the Identify data 00368 // 00369 PCIIDE_UDMA_MODES_SUPPORTED PciIdeUdmaModesSupported; 00370 00371 } IDE_CONTROLLER_PROPERTIES, *PIDE_CONTROLLER_PROPERTIES; 00372 00373 // 00374 // callback to query PCI IDE controller properties 00375 // 00376 typedef 00377 NTSTATUS (*PCONTROLLER_PROPERTIES) ( 00378 IN PVOID DeviceExtension, 00379 IN PIDE_CONTROLLER_PROPERTIES ControllerProperties 00380 ); 00381 00382 00383 // 00384 // To initailize PCI IDE mini driver 00385 // 00386 NTSTATUS 00387 PciIdeXInitialize( 00388 IN PDRIVER_OBJECT DriverObject, 00389 IN PUNICODE_STRING RegistryPath, 00390 IN PCONTROLLER_PROPERTIES PciIdeGetControllerProperties, 00391 IN ULONG ExtensionSize 00392 ); 00393 00394 // 00395 // To query PCI IDE config space data 00396 // 00397 NTSTATUS 00398 PciIdeXGetBusData( 00399 IN PVOID DeviceExtension, 00400 IN PVOID Buffer, 00401 IN ULONG ConfigDataOffset, 00402 IN ULONG BufferLength 00403 ); 00404 00405 // 00406 // To save PCI IDE config space data 00407 // 00408 NTSTATUS 00409 PciIdeXSetBusData( 00410 IN PVOID DeviceExtension, 00411 IN PVOID Buffer, 00412 IN PVOID DataMask, 00413 IN ULONG ConfigDataOffset, 00414 IN ULONG BufferLength 00415 ); 00416 00417 00418 #pragma pack(1) 00419 typedef struct _PCIIDE_CONFIG_HEADER { 00420 00421 USHORT VendorID; // (ro) 00422 USHORT DeviceID; // (ro) 00423 00424 // 00425 // Command 00426 // 00427 union { 00428 00429 struct { 00430 00431 USHORT IoAccessEnable:1; // Device control 00432 USHORT MemAccessEnable:1; 00433 USHORT MasterEnable:1; 00434 USHORT SpecialCycle:1; 00435 USHORT MemWriteInvalidateEnable:1; 00436 USHORT VgaPaletteSnoopEnable:1; 00437 USHORT ParityErrorResponse:1; 00438 USHORT WaitCycleEnable:1; 00439 USHORT SystemErrorEnable:1; 00440 USHORT FastBackToBackEnable:1; 00441 USHORT CommandReserved:6; 00442 } b; 00443 00444 USHORT w; 00445 00446 } Command; 00447 00448 00449 USHORT Status; 00450 UCHAR RevisionID; // (ro) 00451 00452 // 00453 // Program Interface 00454 // 00455 UCHAR Chan0OpMode:1; 00456 UCHAR Chan0Programmable:1; 00457 UCHAR Chan1OpMode:1; 00458 UCHAR Chan1Programmable:1; 00459 UCHAR ProgIfReserved:3; 00460 UCHAR MasterIde:1; 00461 00462 UCHAR SubClass; // (ro) 00463 UCHAR BaseClass; // (ro) 00464 UCHAR CacheLineSize; // (ro+) 00465 UCHAR LatencyTimer; // (ro+) 00466 UCHAR HeaderType; // (ro) 00467 UCHAR BIST; // Built in self test 00468 00469 struct _PCI_HEADER_TYPE_0 type0; 00470 00471 } PCIIDE_CONFIG_HEADER, *PPCIIDE_CONFIG_HEADER; 00472 #pragma pack() 00473 00474 // 00475 // Debug Print 00476 // 00477 #if DBG 00478 00479 VOID 00480 PciIdeXDebugPrint( 00481 ULONG DebugPrintLevel, 00482 PCCHAR DebugMessage, 00483 ... 00484 ); 00485 00486 #define PciIdeXDebugPrint(x) PciIdeXDebugPrint x 00487 00488 #else 00489 00490 #define PciIdeXDebugPrint(x) 00491 00492 #endif // DBG 00493 00494 #endif // ___ide_h___ 00495
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