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ReactOS Development > Doxygen

compat.h
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00001 #pragma once
00002 
00003 #define __init
00004 #define __initdata
00005 
00006 #define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
00007 #define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
00008 #define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
00009 #define SPRN_LDSTDB     0x3f4   /* */
00010 #define SPRN_LR         0x008   /* Link Register */
00011 #ifndef SPRN_PIR
00012 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
00013 #endif
00014 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
00015 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
00016 #define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
00017 #define SPRN_PVR        0x11F   /* Processor Version Register */
00018 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
00019 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
00020 #define SPRN_SDR1       0x019   /* MMU Hash Base Register */
00021 #define SPRN_ASR        0x118   /* Address Space Register */
00022 #define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
00023 #define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
00024 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
00025 #define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
00026 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
00027 #define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
00028 #define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
00029 #define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
00030 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
00031 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
00032 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
00033 #ifndef SPRN_SVR
00034 #define SPRN_SVR        0x11E   /* System Version Register */
00035 #endif
00036 #define SPRN_THRM1      0x3FC           /* Thermal Management Register 1 */
00037 /* these bits were defined in inverted endian sense originally, ugh, confusing */
00038 
00039 /* Values for PP (assumes Ks=0, Kp=1) */
00040 #define PP_RWXX 0       /* Supervisor read/write, User none */
00041 #define PP_RWRX 1       /* Supervisor read/write, User read */
00042 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
00043 #define PP_RXRX 3       /* Supervisor read,       User read */
00044 
00045 /* Block size masks */
00046 #define BL_128K 0x000
00047 #define BL_256K 0x001
00048 #define BL_512K 0x003
00049 #define BL_1M   0x007
00050 #define BL_2M   0x00F
00051 #define BL_4M   0x01F
00052 #define BL_8M   0x03F
00053 #define BL_16M  0x07F
00054 #define BL_32M  0x0FF
00055 #define BL_64M  0x1FF
00056 #define BL_128M 0x3FF
00057 #define BL_256M 0x7FF
00058 
00059 /* BAT Access Protection */
00060 #define BPP_XX  0x00            /* No access */
00061 #define BPP_RX  0x01            /* Read only */
00062 #define BPP_RW  0x02            /* Read/write */
00063 
00064 /* Definitions for 40x embedded chips. */
00065 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
00066 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
00067 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
00068 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
00069 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
00070 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
00071 #define _PAGE_RW        0x040   /* software: Writes permitted */
00072 #define _PAGE_DIRTY     0x080   /* software: dirty page */
00073 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
00074 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
00075 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
00076 
00077 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
00078 #define _PMD_BAD        0x802
00079 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
00080 #define _PMD_SIZE_4M    0x0c0
00081 #define _PMD_SIZE_16M   0x0e0
00082 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
00083 
00084 #define PVR_VER(pvr)(((pvr) >>  16) & 0xFFFF) /* Version field */
00085 
00086 #define KERNELBASE 0x80000000
00087 
00088 typedef unsigned char __u8;
00089 typedef unsigned short __u16;
00090 typedef unsigned int __u32;
00091 
00092 typedef struct _pci_reg_property {
00093     struct {
00094     int a_hi, a_mid, a_lo;
00095     } addr;
00096     int size_hi, size_lo;
00097 } pci_reg_property;
00098 
00099 void btext_drawstring(const char *c);
00100 void btext_drawhex(unsigned long v);
00101 
00102 void *ioremap(__u32 phys, __u32 size);
00103 void iounmap(void *logical);
00104 
00105 __u32 GetPVR(void);

Generated on Sun May 27 2012 04:19:09 for ReactOS by doxygen 1.7.6.1

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