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ReactOS Development > Doxygenrs232.c
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00001 /* 00002 * FreeLoader 00003 * Copyright (C) 2001 Brian Palmer <brianp@sginet.com> 00004 * Copyright (C) 2001 Eric Kohl 00005 * Copyright (C) 2001 Emanuele Aliberti 00006 * 00007 * This program is free software; you can redistribute it and/or modify 00008 * it under the terms of the GNU General Public License as published by 00009 * the Free Software Foundation; either version 2 of the License, or 00010 * (at your option) any later version. 00011 * 00012 * This program is distributed in the hope that it will be useful, 00013 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00015 * GNU General Public License for more details. 00016 * 00017 * You should have received a copy of the GNU General Public License along 00018 * with this program; if not, write to the Free Software Foundation, Inc., 00019 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 00020 */ 00021 00022 #ifndef _M_ARM 00023 00024 #include <freeldr.h> 00025 00026 /* MACROS *******************************************************************/ 00027 00028 #if DBG 00029 00030 #define DEFAULT_BAUD_RATE 19200 00031 00032 #define SER_RBR(x) ((x)+0) 00033 #define SER_THR(x) ((x)+0) 00034 #define SER_DLL(x) ((x)+0) 00035 #define SER_IER(x) ((x)+1) 00036 #define SER_DLM(x) ((x)+1) 00037 #define SER_IIR(x) ((x)+2) 00038 #define SER_LCR(x) ((x)+3) 00039 #define SR_LCR_CS5 0x00 00040 #define SR_LCR_CS6 0x01 00041 #define SR_LCR_CS7 0x02 00042 #define SR_LCR_CS8 0x03 00043 #define SR_LCR_ST1 0x00 00044 #define SR_LCR_ST2 0x04 00045 #define SR_LCR_PNO 0x00 00046 #define SR_LCR_POD 0x08 00047 #define SR_LCR_PEV 0x18 00048 #define SR_LCR_PMK 0x28 00049 #define SR_LCR_PSP 0x38 00050 #define SR_LCR_BRK 0x40 00051 #define SR_LCR_DLAB 0x80 00052 #define SER_MCR(x) ((x)+4) 00053 #define SR_MCR_DTR 0x01 00054 #define SR_MCR_RTS 0x02 00055 #define SER_LSR(x) ((x)+5) 00056 #define SR_LSR_DR 0x01 00057 #define SR_LSR_TBE 0x20 00058 #define SER_MSR(x) ((x)+6) 00059 #define SR_MSR_CTS 0x10 00060 #define SR_MSR_DSR 0x20 00061 #define SER_SCR(x) ((x)+7) 00062 00063 /* STATIC VARIABLES *********************************************************/ 00064 00065 static ULONG Rs232ComPort = 0; 00066 static ULONG Rs232BaudRate = 0; 00067 static PUCHAR Rs232PortBase = (PUCHAR)0; 00068 00069 /* The com port must only be initialized once! */ 00070 static BOOLEAN PortInitialized = FALSE; 00071 00072 /* STATIC FUNCTIONS *********************************************************/ 00073 00074 static BOOLEAN Rs232DoesComPortExist(PUCHAR BaseAddress) 00075 { 00076 BOOLEAN found; 00077 UCHAR mcr; 00078 UCHAR msr; 00079 00080 found = FALSE; 00081 00082 /* save Modem Control Register (MCR) */ 00083 mcr = READ_PORT_UCHAR (SER_MCR(BaseAddress)); 00084 00085 /* enable loop mode (set Bit 4 of the MCR) */ 00086 WRITE_PORT_UCHAR (SER_MCR(BaseAddress), 0x10); 00087 00088 /* clear all modem output bits */ 00089 WRITE_PORT_UCHAR (SER_MCR(BaseAddress), 0x10); 00090 00091 /* read the Modem Status Register */ 00092 msr = READ_PORT_UCHAR (SER_MSR(BaseAddress)); 00093 00094 /* 00095 * the upper nibble of the MSR (modem output bits) must be 00096 * equal to the lower nibble of the MCR (modem input bits) 00097 */ 00098 if ((msr & 0xF0) == 0x00) 00099 { 00100 /* set all modem output bits */ 00101 WRITE_PORT_UCHAR (SER_MCR(BaseAddress), 0x1F); 00102 00103 /* read the Modem Status Register */ 00104 msr = READ_PORT_UCHAR (SER_MSR(BaseAddress)); 00105 00106 /* 00107 * the upper nibble of the MSR (modem output bits) must be 00108 * equal to the lower nibble of the MCR (modem input bits) 00109 */ 00110 if ((msr & 0xF0) == 0xF0) 00111 found = TRUE; 00112 } 00113 00114 /* restore MCR */ 00115 WRITE_PORT_UCHAR (SER_MCR(BaseAddress), mcr); 00116 00117 return (found); 00118 } 00119 00120 /* FUNCTIONS *********************************************************/ 00121 00122 BOOLEAN Rs232PortInitialize(ULONG ComPort, ULONG BaudRate) 00123 { 00124 ULONG BaseArray[5] = {0, 0x3F8, 0x2F8, 0x3E8, 0x2E8}; 00125 //char buffer[80]; 00126 ULONG divisor; 00127 UCHAR lcr; 00128 00129 if (PortInitialized == FALSE) 00130 { 00131 if (BaudRate != 0) 00132 { 00133 Rs232BaudRate = BaudRate; 00134 } 00135 else 00136 { 00137 Rs232BaudRate = DEFAULT_BAUD_RATE; 00138 } 00139 00140 if (ComPort == 0) 00141 { 00142 if (Rs232DoesComPortExist ((PUCHAR)(ULONG_PTR)BaseArray[2])) 00143 { 00144 Rs232PortBase = (PUCHAR)(ULONG_PTR)BaseArray[2]; 00145 Rs232ComPort = 2; 00146 /*#ifndef NDEBUG 00147 sprintf (buffer, 00148 "\nSerial port COM%ld found at 0x%lx\n", 00149 ComPort, 00150 (ULONG)PortBase); 00151 HalDisplayString (buffer); 00152 #endif*/ /* NDEBUG */ 00153 } 00154 else if (Rs232DoesComPortExist ((PUCHAR)(ULONG_PTR)BaseArray[1])) 00155 { 00156 Rs232PortBase = (PUCHAR)(ULONG_PTR)BaseArray[1]; 00157 Rs232ComPort = 1; 00158 /*#ifndef NDEBUG 00159 sprintf (buffer, 00160 "\nSerial port COM%ld found at 0x%lx\n", 00161 ComPort, 00162 (ULONG)PortBase); 00163 HalDisplayString (buffer); 00164 #endif*/ /* NDEBUG */ 00165 } 00166 else 00167 { 00168 /*sprintf (buffer, 00169 "\nKernel Debugger: No COM port found!!!\n\n"); 00170 HalDisplayString (buffer);*/ 00171 return FALSE; 00172 } 00173 } 00174 else 00175 { 00176 if (Rs232DoesComPortExist ((PUCHAR)(ULONG_PTR)BaseArray[ComPort])) 00177 { 00178 Rs232PortBase = (PUCHAR)(ULONG_PTR)BaseArray[ComPort]; 00179 Rs232ComPort = ComPort; 00180 /*#ifndef NDEBUG 00181 sprintf (buffer, 00182 "\nSerial port COM%ld found at 0x%lx\n", 00183 ComPort, 00184 (ULONG)PortBase); 00185 HalDisplayString (buffer); 00186 #endif*/ /* NDEBUG */ 00187 } 00188 else 00189 { 00190 /*sprintf (buffer, 00191 "\nKernel Debugger: No serial port found!!!\n\n"); 00192 HalDisplayString (buffer);*/ 00193 return FALSE; 00194 } 00195 } 00196 00197 PortInitialized = TRUE; 00198 } 00199 00200 /* 00201 * set baud rate and data format (8N1) 00202 */ 00203 00204 /* turn on DTR and RTS */ 00205 WRITE_PORT_UCHAR (SER_MCR(Rs232PortBase), SR_MCR_DTR | SR_MCR_RTS); 00206 00207 /* set DLAB */ 00208 lcr = READ_PORT_UCHAR (SER_LCR(Rs232PortBase)) | SR_LCR_DLAB; 00209 WRITE_PORT_UCHAR (SER_LCR(Rs232PortBase), lcr); 00210 00211 /* set baud rate */ 00212 divisor = 115200 / BaudRate; 00213 WRITE_PORT_UCHAR (SER_DLL(Rs232PortBase), divisor & 0xff); 00214 WRITE_PORT_UCHAR (SER_DLM(Rs232PortBase), (divisor >> 8) & 0xff); 00215 00216 /* reset DLAB and set 8N1 format */ 00217 WRITE_PORT_UCHAR (SER_LCR(Rs232PortBase), 00218 SR_LCR_CS8 | SR_LCR_ST1 | SR_LCR_PNO); 00219 00220 /* read junk out of the RBR */ 00221 lcr = READ_PORT_UCHAR (SER_RBR(Rs232PortBase)); 00222 00223 /* 00224 * set global info 00225 */ 00226 //KdComPortInUse = (ULONG)PortBase; 00227 00228 /* 00229 * print message to blue screen 00230 */ 00231 /*sprintf (buffer, 00232 "\nKernel Debugger: COM%ld (Port 0x%lx) BaudRate %ld\n\n", 00233 ComPort, 00234 (ULONG)PortBase, 00235 BaudRate); 00236 00237 HalDisplayString (buffer);*/ 00238 00239 return TRUE; 00240 } 00241 00242 BOOLEAN Rs232PortGetByte(PUCHAR ByteRecieved) 00243 { 00244 if (PortInitialized == FALSE) 00245 return FALSE; 00246 00247 if ((READ_PORT_UCHAR (SER_LSR(Rs232PortBase)) & SR_LSR_DR)) 00248 { 00249 *ByteRecieved = READ_PORT_UCHAR (SER_RBR(Rs232PortBase)); 00250 return TRUE; 00251 } 00252 00253 return FALSE; 00254 } 00255 00256 BOOLEAN Rs232PortPollByte(PUCHAR ByteRecieved) 00257 { 00258 if (PortInitialized == FALSE) 00259 return FALSE; 00260 00261 while ((READ_PORT_UCHAR (SER_LSR(Rs232PortBase)) & SR_LSR_DR) == 0) 00262 ; 00263 00264 *ByteRecieved = READ_PORT_UCHAR (SER_RBR(Rs232PortBase)); 00265 00266 return TRUE; 00267 } 00268 00269 VOID Rs232PortPutByte(UCHAR ByteToSend) 00270 { 00271 if (PortInitialized == FALSE) 00272 return; 00273 00274 while ((READ_PORT_UCHAR (SER_LSR(Rs232PortBase)) & SR_LSR_TBE) == 0) 00275 ; 00276 00277 WRITE_PORT_UCHAR (SER_THR(Rs232PortBase), ByteToSend); 00278 } 00279 00280 #endif /* DBG */ 00281 00282 BOOLEAN Rs232PortInUse(ULONG Base) 00283 { 00284 #if DBG 00285 return PortInitialized && Rs232PortBase == (PUCHAR)(ULONG_PTR)Base ? TRUE : FALSE; 00286 #else 00287 return FALSE; 00288 #endif 00289 } 00290 00291 #endif /* not _M_ARM */ Generated on Sun May 27 2012 04:19:07 for ReactOS by
1.7.6.1
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