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ReactOS Development > Doxygen

midiuart.h
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00001 /*
00002     ReactOS Sound System
00003     MIDI UART support
00004 
00005     Author:
00006         Andrew Greenwood (silverblade@reactos.org)
00007 
00008     History:
00009         26 May 2008 - Created
00010 
00011     Notes:
00012         MIDI UART is fairly simple. There are two ports - one is a data
00013         port and is read/write, the other is a command/status port where
00014         you can write commands, and read status.
00015 
00016         We use a subset of the functionality offered by the original MPU-401
00017         hardware, which is pretty much the only part implemented in sound
00018         cards these days, known as "MIDI UART" mode.
00019 */
00020 
00021 #ifndef ROS_MIDIUART
00022 #define ROS_MIDIUART
00023 
00024 /* Port read/write abstraction (no wait) */
00025 #define WRITE_MIDIUART_DATA(bp, x)      WRITE_PORT_UCHAR((PUCHAR) bp, x)
00026 #define READ_MIDIUART_DATA(bp)          READ_PORT_UCHAR((PUCHAR) bp)
00027 #define WRITE_MIDIUART_COMMAND(bp, x)   WRITE_PORT_UCHAR((PUCHAR) bp+1, x)
00028 #define READ_MIDIUART_STATUS(bp)        READ_PORT_UCHAR((PUCHAR) bp+1)
00029 
00030 /* Status flags */
00031 #define MIDIUART_STATUS_DTR             0x40
00032 #define MIDIUART_STATUS_CTS             0x80
00033 
00034 
00035 /*
00036     WaitForMidiUartStatus
00037 
00038     A universal routine for waiting for one or more bits to be set on the
00039     MIDI UART command/status port. (Not a particularly efficient wait as
00040     this polls the port until it's ready!)
00041 
00042     If the timeout is reached, the function returns FALSE. Otherwise, when
00043     the specified flag(s) become set, the function returns TRUE.
00044 */
00045 
00046 BOOLEAN
00047 WaitForMidiUartStatus(
00048     IN  PUCHAR UartBasePort,
00049     IN  UCHAR StatusFlags,
00050     IN  ULONG Timeout);
00051 
00052 /* Waits for the CTS status bit to be set */
00053 #define WaitForMidiUartCTS(UartBasePort, Timeout) \
00054     WaitForMidiUartStatus(UartBasePort, MIDIUART_STATUS_CTS, Timeout)
00055 
00056 /* Waits for the DTR status bit to be set */
00057 #define WaitForMidiUartDTR(UartBasePort, Timeout) \
00058     WaitForMidiUartStatus(UartBasePort, MIDIUART_STATUS_DTR, Timeout)
00059 
00060 /*
00061     WriteMidiUartByte
00062 
00063     Wait for the CTS bit to be set on the command/status port, before
00064     writing to the data port. If CTS does not get set within the timeout
00065     period, returns FALSE. Otherwise, returns TRUE.
00066 */
00067 
00068 BOOLEAN
00069 WriteMidiUartByte(
00070     IN  PUCHAR UartBasePort,
00071     IN  UCHAR Data,
00072     IN  ULONG Timeout);
00073 
00074 
00075 /*
00076     WriteMidiUartMulti
00077 
00078     Write multiple bytes to the MIDI UART data port. The timeout applies on a
00079     per-byte basis. If it is reached for any byte, the function will return
00080     FALSE.
00081 
00082     All data is written "as-is" - there are no checks made as to the validity
00083     of the data.
00084 */
00085 
00086 BOOLEAN
00087 WriteMidiUartMulti(
00088     IN  PUCHAR UartBasePort,
00089     IN  PUCHAR Data,
00090     IN  ULONG DataLength,
00091     IN  ULONG Timeout);
00092 
00093 
00094 /*
00095     ReadMidiUartByte
00096 
00097     Wait for the DTR bit to be set on the command/status port, before
00098     reading from the data port. If DTR does not get set within the
00099     timeout period, returns FALSE. Otherwise, returns TRUE.
00100 
00101     On success, the read data is stored in the location specified by
00102     the Data parameter.
00103 */
00104 
00105 BOOLEAN
00106 ReadMidiUartByte(
00107     IN  PUCHAR UartBasePort,
00108     OUT UCHAR* Data,
00109     IN  ULONG Timeout);
00110 
00111 #endif

Generated on Sun May 27 2012 04:33:16 for ReactOS by doxygen 1.7.6.1

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