ReactOS Development > Doxygen
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Definition at line 43 of file kdcom.c. Referenced by KdDebuggerInitialize0(). {
ULONG Mode;
KDDBGPRINT("KdpPortInitialize, Port = COM%ld\n", ComPortNumber);
/* Enable loop mode (set Bit 4 of the MCR) */
WRITE_PORT_UCHAR(ComPortBase + COM_MCR, MCR_LOOP);
/* Clear all modem output bits */
WRITE_PORT_UCHAR(ComPortBase + COM_MCR, MCR_LOOP);
/* The upper nibble of the MSR (modem output bits) must be
* equal to the lower nibble of the MCR (modem input bits) */
if ((READ_PORT_UCHAR(ComPortBase + COM_MSR) & 0xF0) != 0x00)
{
return STATUS_INVALID_PARAMETER;
}
/* Set all modem output bits */
WRITE_PORT_UCHAR(ComPortBase + COM_MCR, MCR_ALL);
/* The upper nibble of the MSR (modem output bits) must be
* equal to the lower nibble of the MCR (modem input bits) */
if ((READ_PORT_UCHAR(ComPortBase + COM_MSR) & 0xF0) != 0xF0)
{
return STATUS_INVALID_PARAMETER;
}
/* Enable FIFO */
WRITE_PORT_UCHAR(ComPortBase + COM_FCR,
FCR_ENABLE_FIFO | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT);
/* Disable interrupts */
WRITE_PORT_UCHAR(ComPortBase + COM_LCR, 0);
WRITE_PORT_UCHAR(ComPortBase + COM_IEN, 0);
/* Enable on DTR and RTS */
WRITE_PORT_UCHAR(ComPortBase + COM_MCR, MCR_DTR | MCR_RTS);
/* Set DLAB */
WRITE_PORT_UCHAR(ComPortBase + COM_LCR, LCR_DLAB);
/* Set baud rate */
Mode = 115200 / ComPortBaudRate;
WRITE_PORT_UCHAR(ComPortBase + COM_DLL, (UCHAR)(Mode & 0xff));
WRITE_PORT_UCHAR(ComPortBase + COM_DLM, (UCHAR)((Mode >> 8) & 0xff));
/* Reset DLAB and set 8 data bits, 1 stop bit, no parity, no break */
WRITE_PORT_UCHAR(ComPortBase + COM_LCR, LCR_CS8 | LCR_ST1 | LCR_PNO);
/* Check for 16450/16550 scratch register */
WRITE_PORT_UCHAR(ComPortBase + COM_SCR, 0xff);
if (READ_PORT_UCHAR(ComPortBase + COM_SCR) != 0xff)
{
return STATUS_INVALID_PARAMETER;
}
WRITE_PORT_UCHAR(ComPortBase + COM_SCR, 0x00);
if (READ_PORT_UCHAR(ComPortBase + COM_SCR) != 0x00)
{
return STATUS_INVALID_PARAMETER;
}
return STATUS_SUCCESS;
}
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Generated on Sat May 26 2012 05:20:29 for ReactOS by
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