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haldma.h
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00001 #pragma once 00002 00003 /* 00004 * DMA Page Register Structure 00005 * 080 DMA RESERVED 00006 * 081 DMA Page Register (channel 2) 00007 * 082 DMA Page Register (channel 3) 00008 * 083 DMA Page Register (channel 1) 00009 * 084 DMA RESERVED 00010 * 085 DMA RESERVED 00011 * 086 DMA RESERVED 00012 * 087 DMA Page Register (channel 0) 00013 * 088 DMA RESERVED 00014 * 089 PS/2-DMA Page Register (channel 6) 00015 * 08A PS/2-DMA Page Register (channel 7) 00016 * 08B PS/2-DMA Page Register (channel 5) 00017 * 08C PS/2-DMA RESERVED 00018 * 08D PS/2-DMA RESERVED 00019 * 08E PS/2-DMA RESERVED 00020 * 08F PS/2-DMA Page Register (channel 4) 00021 */ 00022 00023 typedef struct _DMA_PAGE 00024 { 00025 UCHAR Reserved1; 00026 UCHAR Channel2; 00027 UCHAR Channel3; 00028 UCHAR Channel1; 00029 UCHAR Reserved2[3]; 00030 UCHAR Channel0; 00031 UCHAR Reserved3; 00032 UCHAR Channel6; 00033 UCHAR Channel7; 00034 UCHAR Channel5; 00035 UCHAR Reserved4[3]; 00036 UCHAR Channel4; 00037 } DMA_PAGE, *PDMA_PAGE; 00038 00039 /* 00040 * DMA Channel Mask Register Structure 00041 * 00042 * MSB LSB 00043 * x x x x x x x x 00044 * ------------------- - ----- 00045 * | | | 00 - Select channel 0 mask bit 00046 * | | \---- 01 - Select channel 1 mask bit 00047 * | | 10 - Select channel 2 mask bit 00048 * | | 11 - Select channel 3 mask bit 00049 * | | 00050 * | \---------- 0 - Clear mask bit 00051 * | 1 - Set mask bit 00052 * | 00053 * \----------------------- xx - Reserved 00054 */ 00055 00056 typedef struct _DMA_CHANNEL_MASK 00057 { 00058 UCHAR Channel: 2; 00059 UCHAR SetMask: 1; 00060 UCHAR Reserved: 5; 00061 } DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK; 00062 00063 /* 00064 * DMA Mask Register Structure 00065 * 00066 * MSB LSB 00067 * x x x x x x x x 00068 * \---/ - - ----- ----- 00069 * | | | | | 00 - Channel 0 select 00070 * | | | | \---- 01 - Channel 1 select 00071 * | | | | 10 - Channel 2 select 00072 * | | | | 11 - Channel 3 select 00073 * | | | | 00074 * | | | | 00 - Verify transfer 00075 * | | | \------------ 01 - Write transfer 00076 * | | | 10 - Read transfer 00077 * | | | 00078 * | | \-------------------- 0 - Autoinitialized 00079 * | | 1 - Non-autoinitialized 00080 * | | 00081 * | \------------------------ 0 - Address increment select 00082 * | 00083 * | 00 - Demand mode 00084 * \------------------------------ 01 - Single mode 00085 * 10 - Block mode 00086 * 11 - Cascade mode 00087 */ 00088 00089 typedef union _DMA_MODE 00090 { 00091 struct 00092 { 00093 UCHAR Channel: 2; 00094 UCHAR TransferType: 2; 00095 UCHAR AutoInitialize: 1; 00096 UCHAR AddressDecrement: 1; 00097 UCHAR RequestMode: 2; 00098 }; 00099 UCHAR Byte; 00100 } DMA_MODE, *PDMA_MODE; 00101 00102 /* 00103 * DMA Extended Mode Register Structure 00104 * 00105 * MSB LSB 00106 * x x x x x x x x 00107 * - - ----- ----- ----- 00108 * | | | | | 00 - Channel 0 select 00109 * | | | | \---- 01 - Channel 1 select 00110 * | | | | 10 - Channel 2 select 00111 * | | | | 11 - Channel 3 select 00112 * | | | | 00113 * | | | | 00 - 8-bit I/O, by bytes 00114 * | | | \------------ 01 - 16-bit I/O, by words, address shifted 00115 * | | | 10 - 32-bit I/O, by bytes 00116 * | | | 11 - 16-bit I/O, by bytes 00117 * | | | 00118 * | | \---------------------- 00 - Compatible 00119 * | | 01 - Type A 00120 * | | 10 - Type B 00121 * | | 11 - Burst 00122 * | | 00123 * | \---------------------------- 0 - Terminal Count is Output 00124 * | 00125 * \---------------------------------0 - Disable Stop Register 00126 * 1 - Enable Stop Register 00127 */ 00128 00129 typedef union _DMA_EXTENDED_MODE 00130 { 00131 struct 00132 { 00133 UCHAR ChannelNumber: 2; 00134 UCHAR TransferSize: 2; 00135 UCHAR TimingMode: 2; 00136 UCHAR TerminalCountIsOutput: 1; 00137 UCHAR EnableStopRegister: 1; 00138 }; 00139 UCHAR Byte; 00140 } DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE; 00141 00142 /* DMA Extended Mode Register Transfer Sizes */ 00143 #define B_8BITS 0 00144 #define W_16BITS 1 00145 #define B_32BITS 2 00146 #define B_16BITS 3 00147 00148 /* DMA Extended Mode Register Timing */ 00149 #define COMPATIBLE_TIMING 0 00150 #define TYPE_A_TIMING 1 00151 #define TYPE_B_TIMING 2 00152 #define BURST_TIMING 3 00153 00154 /* Channel Stop Registers for each Channel */ 00155 typedef struct _DMA_CHANNEL_STOP 00156 { 00157 UCHAR ChannelLow; 00158 UCHAR ChannelMid; 00159 UCHAR ChannelHigh; 00160 UCHAR Reserved; 00161 } DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP; 00162 00163 /* Transfer Types */ 00164 #define VERIFY_TRANSFER 0x00 00165 #define READ_TRANSFER 0x01 00166 #define WRITE_TRANSFER 0x02 00167 00168 /* Request Modes */ 00169 #define DEMAND_REQUEST_MODE 0x00 00170 #define SINGLE_REQUEST_MODE 0x01 00171 #define BLOCK_REQUEST_MODE 0x02 00172 #define CASCADE_REQUEST_MODE 0x03 00173 00174 #define DMA_SETMASK 4 00175 #define DMA_CLEARMASK 0 00176 #define DMA_READ 4 00177 #define DMA_WRITE 8 00178 #define DMA_SINGLE_TRANSFER 0x40 00179 #define DMA_AUTO_INIT 0x10 00180 00181 typedef struct _DMA1_ADDRESS_COUNT 00182 { 00183 UCHAR DmaBaseAddress; 00184 UCHAR DmaBaseCount; 00185 } DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT; 00186 00187 typedef struct _DMA2_ADDRESS_COUNT 00188 { 00189 UCHAR DmaBaseAddress; 00190 UCHAR Reserved1; 00191 UCHAR DmaBaseCount; 00192 UCHAR Reserved2; 00193 } DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT; 00194 00195 typedef struct _DMA1_CONTROL 00196 { 00197 DMA1_ADDRESS_COUNT DmaAddressCount[4]; 00198 UCHAR DmaStatus; 00199 UCHAR DmaRequest; 00200 UCHAR SingleMask; 00201 UCHAR Mode; 00202 UCHAR ClearBytePointer; 00203 UCHAR MasterClear; 00204 UCHAR ClearMask; 00205 UCHAR AllMask; 00206 } DMA1_CONTROL, *PDMA1_CONTROL; 00207 00208 typedef struct _DMA2_CONTROL 00209 { 00210 DMA2_ADDRESS_COUNT DmaAddressCount[4]; 00211 UCHAR DmaStatus; 00212 UCHAR Reserved1; 00213 UCHAR DmaRequest; 00214 UCHAR Reserved2; 00215 UCHAR SingleMask; 00216 UCHAR Reserved3; 00217 UCHAR Mode; 00218 UCHAR Reserved4; 00219 UCHAR ClearBytePointer; 00220 UCHAR Reserved5; 00221 UCHAR MasterClear; 00222 UCHAR Reserved6; 00223 UCHAR ClearMask; 00224 UCHAR Reserved7; 00225 UCHAR AllMask; 00226 UCHAR Reserved8; 00227 } DMA2_CONTROL, *PDMA2_CONTROL; 00228 00229 /* This structure defines the I/O Map of the 82537 controller. */ 00230 typedef struct _EISA_CONTROL 00231 { 00232 /* DMA Controller 1 */ 00233 DMA1_CONTROL DmaController1; /* 00h-0Fh */ 00234 UCHAR Reserved1[16]; /* 0Fh-1Fh */ 00235 00236 /* Interrupt Controller 1 (PIC) */ 00237 UCHAR Pic1Operation; /* 20h */ 00238 UCHAR Pic1Interrupt; /* 21h */ 00239 UCHAR Reserved2[30]; /* 22h-3Fh */ 00240 00241 /* Timer */ 00242 UCHAR TimerCounter; /* 40h */ 00243 UCHAR TimerMemoryRefresh; /* 41h */ 00244 UCHAR Speaker; /* 42h */ 00245 UCHAR TimerOperation; /* 43h */ 00246 UCHAR TimerMisc; /* 44h */ 00247 UCHAR Reserved3[2]; /* 45-46h */ 00248 UCHAR TimerCounterControl; /* 47h */ 00249 UCHAR TimerFailSafeCounter; /* 48h */ 00250 UCHAR Reserved4; /* 49h */ 00251 UCHAR TimerCounter2; /* 4Ah */ 00252 UCHAR TimerOperation2; /* 4Bh */ 00253 UCHAR Reserved5[20]; /* 4Ch-5Fh */ 00254 00255 /* NMI / Keyboard / RTC */ 00256 UCHAR Keyboard; /* 60h */ 00257 UCHAR NmiStatus; /* 61h */ 00258 UCHAR Reserved6[14]; /* 62h-6Fh */ 00259 UCHAR NmiEnable; /* 70h */ 00260 UCHAR Reserved7[15]; /* 71h-7Fh */ 00261 00262 /* DMA Page Registers Controller 1 */ 00263 DMA_PAGE DmaController1Pages; /* 80h-8Fh */ 00264 UCHAR Reserved8[16]; /* 90h-9Fh */ 00265 00266 /* Interrupt Controller 2 (PIC) */ 00267 UCHAR Pic2Operation; /* 0A0h */ 00268 UCHAR Pic2Interrupt; /* 0A1h */ 00269 UCHAR Reserved9[30]; /* 0A2h-0BFh */ 00270 00271 /* DMA Controller 2 */ 00272 DMA1_CONTROL DmaController2; /* 0C0h-0CFh */ 00273 00274 /* System Reserved Ports */ 00275 UCHAR SystemReserved[816]; /* 0D0h-3FFh */ 00276 00277 /* Extended DMA Registers, Controller 1 */ 00278 UCHAR DmaHighByteCount1[8]; /* 400h-407h */ 00279 UCHAR Reserved10[2]; /* 408h-409h */ 00280 UCHAR DmaChainMode1; /* 40Ah */ 00281 UCHAR DmaExtendedMode1; /* 40Bh */ 00282 UCHAR DmaBufferControl; /* 40Ch */ 00283 UCHAR Reserved11[84]; /* 40Dh-460h */ 00284 UCHAR ExtendedNmiControl; /* 461h */ 00285 UCHAR NmiCommand; /* 462h */ 00286 UCHAR Reserved12; /* 463h */ 00287 UCHAR BusMaster; /* 464h */ 00288 UCHAR Reserved13[27]; /* 465h-47Fh */ 00289 00290 /* DMA Page Registers Controller 2 */ 00291 DMA_PAGE DmaController2Pages; /* 480h-48Fh */ 00292 UCHAR Reserved14[48]; /* 490h-4BFh */ 00293 00294 /* Extended DMA Registers, Controller 2 */ 00295 UCHAR DmaHighByteCount2[16]; /* 4C0h-4CFh */ 00296 00297 /* Edge/Level Control Registers */ 00298 UCHAR Pic1EdgeLevel; /* 4D0h */ 00299 UCHAR Pic2EdgeLevel; /* 4D1h */ 00300 UCHAR Reserved15[2]; /* 4D2h-4D3h */ 00301 00302 /* Extended DMA Registers, Controller 2 */ 00303 UCHAR DmaChainMode2; /* 4D4h */ 00304 UCHAR Reserved16; /* 4D5h */ 00305 UCHAR DmaExtendedMode2; /* 4D6h */ 00306 UCHAR Reserved17[9]; /* 4D7h-4DFh */ 00307 00308 /* DMA Stop Registers */ 00309 DMA_CHANNEL_STOP DmaChannelStop[8]; /* 4E0h-4FFh */ 00310 } EISA_CONTROL, *PEISA_CONTROL; 00311 00312 typedef struct _ROS_MAP_REGISTER_ENTRY 00313 { 00314 PVOID VirtualAddress; 00315 PHYSICAL_ADDRESS PhysicalAddress; 00316 ULONG Counter; 00317 } ROS_MAP_REGISTER_ENTRY, *PROS_MAP_REGISTER_ENTRY; 00318 00319 typedef struct _ADAPTER_OBJECT { 00320 /* 00321 * New style DMA object definition. The fact that it is at the beginning 00322 * of the ADAPTER_OBJECT structure allows us to easily implement the 00323 * fallback implementation of IoGetDmaAdapter. 00324 */ 00325 DMA_ADAPTER DmaHeader; 00326 00327 /* 00328 * For normal adapter objects pointer to master adapter that takes care 00329 * of channel allocation. For master adapter set to NULL. 00330 */ 00331 struct _ADAPTER_OBJECT *MasterAdapter; 00332 00333 ULONG MapRegistersPerChannel; 00334 PVOID AdapterBaseVa; 00335 PROS_MAP_REGISTER_ENTRY MapRegisterBase; 00336 00337 ULONG NumberOfMapRegisters; 00338 ULONG CommittedMapRegisters; 00339 00340 PWAIT_CONTEXT_BLOCK CurrentWcb; 00341 KDEVICE_QUEUE ChannelWaitQueue; 00342 PKDEVICE_QUEUE RegisterWaitQueue; 00343 LIST_ENTRY AdapterQueue; 00344 KSPIN_LOCK SpinLock; 00345 PRTL_BITMAP MapRegisters; 00346 PUCHAR PagePort; 00347 UCHAR ChannelNumber; 00348 UCHAR AdapterNumber; 00349 USHORT DmaPortAddress; 00350 DMA_MODE AdapterMode; 00351 BOOLEAN NeedsMapRegisters; 00352 BOOLEAN MasterDevice; 00353 BOOLEAN Width16Bits; 00354 BOOLEAN ScatterGather; 00355 BOOLEAN IgnoreCount; 00356 BOOLEAN Dma32BitAddresses; 00357 BOOLEAN Dma64BitAddresses; 00358 LIST_ENTRY AdapterList; 00359 } ADAPTER_OBJECT; 00360 00361 typedef struct _GROW_WORK_ITEM { 00362 WORK_QUEUE_ITEM WorkQueueItem; 00363 PADAPTER_OBJECT AdapterObject; 00364 ULONG NumberOfMapRegisters; 00365 } GROW_WORK_ITEM, *PGROW_WORK_ITEM; 00366 00367 #define MAP_BASE_SW_SG 1 00368 00369 PADAPTER_OBJECT NTAPI 00370 HalpDmaAllocateMasterAdapter(VOID); 00371 00372 PDMA_ADAPTER NTAPI 00373 HalpGetDmaAdapter( 00374 IN PVOID Context, 00375 IN PDEVICE_DESCRIPTION DeviceDescription, 00376 OUT PULONG NumberOfMapRegisters); 00377 00378 ULONG NTAPI 00379 HalpDmaGetDmaAlignment( 00380 PADAPTER_OBJECT AdapterObject);
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