ReactOS Development > Doxygen
hardware.h
Go to the documentation of this file.
00001 /* 00002 * ReactOS Floppy Driver 00003 * Copyright (C) 2004, Vizzini (vizzini@plasmic.com) 00004 * 00005 * This program is free software; you can redistribute it and/or modify 00006 * it under the terms of the GNU General Public License as published by 00007 * the Free Software Foundation; either version 2 of the License, or 00008 * (at your option) any later version. 00009 * 00010 * This program is distributed in the hope that it will be useful, 00011 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 * GNU General Public License for more details. 00014 * 00015 * You should have received a copy of the GNU General Public License along 00016 * with this program; if not, write to the Free Software Foundation, Inc., 00017 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 00018 * 00019 * PROJECT: ReactOS Floppy Driver 00020 * FILE: hardware.h 00021 * PURPOSE: Header for FDC control routines 00022 * PROGRAMMER: Vizzini (vizzini@plasmic.com) 00023 * REVISIONS: 00024 * 15-Feb-2004 vizzini - Created 00025 * 00026 * NOTES: 00027 * - Baesd on http://www.nondot.org/sabre/os/files/Disk/FLOPPY.TXT 00028 * - Some information taken from Intel 82077AA data sheet (order #290166-007) 00029 * - Some definitions are PS/2-Specific; others include the original NEC PD765 00030 * - Other information gathered from the comments in the NT 3.5 floppy driver 00031 * 00032 * TODO: 00033 * - Convert these numbers to 100% absolute values; eliminate bit positions 00034 * in favor of shifts or bitfields 00035 */ 00036 00037 #define FLOPPY_DEFAULT_IRQ 0x6 00038 #define FDC_PORT_BYTES 0x8 00039 00040 /* Register offsets from base address (usually 0x3f8) */ 00041 #define STATUS_REGISTER_A 0x0 /* Read; PS/2 Only */ 00042 #define STATUS_REGISTER_B 0x1 /* Read; PS/2 Only */ 00043 #define DIGITAL_OUTPUT_REGISTER 0x2 /* Read/Write */ 00044 #define TAPE_DRIVE_REGISTER 0x3 /* Read/Write */ 00045 #define MAIN_STATUS_REGISTER 0x4 /* Read */ 00046 #define DATA_RATE_SELECT_REGISTER 0x4 /* Write */ 00047 #define FIFO 0x5 /* Read/Write */ 00048 #define RESERVED_REGISTER 0x6 /* Reserved */ 00049 #define DIGITAL_INPUT_REGISTER 0x7 /* Read; PS/2 Only */ 00050 #define CONFIGURATION_CONTROL_REGISTER 0x7 /* Write; PS/2 Only */ 00051 00052 /* STATUS_REGISTER_A */ 00053 #define DSRA_DIRECTION 0x1 00054 #define DSRA_WRITE_PROTECT 0x2 00055 #define DSRA_INDEX 0x4 00056 #define DSRA_HEAD_1_SELECT 0x8 00057 #define DSRA_TRACK_0 0x10 00058 #define DSRA_STEP 0x20 00059 #define DSRA_SECOND_DRIVE_INSTALLED 0x40 00060 #define DSRA_INTERRUPT_PENDING 0x80 00061 00062 /* STATUS_REGISTER_B */ 00063 #define DSRB_MOTOR_ENABLE_0 0x1 00064 #define DSRB_MOTOR_ENABLE_1 0x2 00065 #define DSRB_WRITE_ENABLE 0x4 00066 #define DSRB_READ_DATA 0x8 00067 #define DSRB_WRTITE_DATA 0x10 00068 #define DSRB_DRIVE_SELECT 0x20 00069 00070 /* DIGITAL_OUTPUT_REGISTER */ 00071 #define DOR_FLOPPY_DRIVE_SELECT 0x3 /* Covers 2 bits, defined below */ 00072 #define DOR_FDC_ENABLE 0x4 /* from the website */ 00073 #define DOR_RESET 0x4 /* from the Intel guide; 0 = resetting, 1 = enabled */ 00074 #define DOR_DMA_IO_INTERFACE_ENABLE 0x8 /* Reserved on PS/2 */ 00075 #define DOR_FLOPPY_MOTOR_ON_A 0x10 00076 #define DOR_FLOPPY_MOTOR_ON_B 0x20 00077 #define DOR_FLOPPY_MOTOR_ON_C 0x40 /* Reserved on PS/2 */ 00078 #define DOR_FLOPPY_MOTOR_ON_D 0x80 /* Reserved on PS/2 */ 00079 00080 /* DOR_FLOPPY_DRIVE_SELECT */ 00081 #define DOR_FLOPPY_DRIVE_SELECT_A 0x0 00082 #define DOR_FLOPPY_DRIVE_SELECT_B 0x1 00083 #define DOR_FLOPPY_DRIVE_SELECT_C 0x2 /* Reserved on PS/2 */ 00084 #define DOR_FLOPPY_DRIVE_SELECT_D 0x3 /* Reserved on PS/2 */ 00085 00086 /* MAIN_STATUS_REGISTER */ 00087 #define MSR_FLOPPY_BUSY_0 0x1 00088 #define MSR_FLOPPY_BUSY_1 0x2 00089 #define MSR_FLOPPY_BUSY_2 0x4 /* Reserved on PS/2 */ 00090 #define MSR_FLOPPY_BUSY_3 0x8 /* Reserved on PS/2 */ 00091 #define MSR_READ_WRITE_IN_PROGRESS 0x10 00092 #define MSR_NON_DMA_MODE 0x20 00093 #define MSR_IO_DIRECTION 0x40 /* Determines meaning of Command Status Registers */ 00094 #define MSR_DATA_REG_READY_FOR_IO 0x80 00095 00096 /* DATA_RATE_SELECT_REGISTER */ 00097 #define DRSR_DSEL 0x3 /* covers two bits as defined below */ 00098 #define DRSR_PRECOMP 0x1c /* covers three bits as defined below */ 00099 #define DRSR_MBZ 0x20 00100 #define DRSR_POWER_DOWN 0x40 00101 #define DRSR_SW_RESET 0x80 00102 00103 /* DRSR_DSEL */ 00104 #define DRSR_DSEL_500KBPS 0x0 00105 #define DRSR_DSEL_300KBPS 0x1 00106 #define DRSR_DSEL_250KBPS 0x2 00107 #define DRSR_DSEL_1MBPS 0x3 00108 00109 /* STATUS_REGISTER_0 */ 00110 #define SR0_UNIT_SELECTED_AT_INTERRUPT 0x3 /* Covers two bits as defined below */ 00111 #define SR0_HEAD_NUMBER_AT_INTERRUPT 0x4 /* Values defined below */ 00112 #define SR0_NOT_READY_ON_READ_WRITE 0x8 /* Unused in PS/2 */ 00113 #define SR0_SS_ACCESS_TO_HEAD_1 0x8 /* Unused in PS/2 */ 00114 #define SR0_EQUIPMENT_CHECK 0x10 00115 #define SR0_SEEK_COMPLETE 0x20 00116 #define SR0_LAST_COMMAND_STATUS 0xC0 /* Covers two bits as defined below */ 00117 00118 /* SR0_UNIT_SELECTED_AT_INTERRUPT */ 00119 #define SR0_UNIT_SELECTED_A 0x0 00120 #define SR0_UNIT_SELECTED_B 0x1 00121 #define SR0_UNIT_SELECTED_C 0x2 00122 #define SR0_UNIT_SELECTED_D 0x3 00123 #define SR0_PS2_UNIT_SELECTED_A 0x1 /* PS/2 uses only two drives: A = 01b B = 10b */ 00124 #define SR0_PST_UNIT_SELECTED_B 0x2 00125 00126 /* SR0_HEAD_NUMBER_AT_INTERRUPT */ 00127 #define SR0_HEAD_0 0x0 00128 #define SR0_HEAD_1 0x1 00129 00130 /* SR0_LAST_COMMAND_STATUS */ 00131 #define SR0_LCS_SUCCESS 0x0 00132 #define SR0_LCS_TERMINATED_ABNORMALLY 0x40 00133 #define SR0_LCS_INVALID_COMMAND_ISSUED 0x80 00134 #define SR0_LCS_READY_SIGNAL_CHANGED 0xc0 /* Reserved on PS/2; a/k/a abnormal termination due to polling */ 00135 00136 /* STATUS_REGISTER_1 */ 00137 #define SR1_CANNOT_FIND_ID_ADDRESS 0x1 /* Mimics SR2_WRONG_CYLINDER_DETECTED */ 00138 #define SR1_WRITE_PROTECT_DETECTED 0x2 00139 #define SR1_CANNOT_FIND_SECTOR_ID 0x4 00140 #define SR1_OVERRUN 0x10 00141 #define SR1_CRC_ERROR 0x20 00142 #define SR1_END_OF_CYLINDER 0x80 00143 00144 /* STATUS_REGISTER_2 */ 00145 #define SR2_MISSING_ADDRESS_MARK 0x1 00146 #define SR2_BAD_CYLINDER 0x2 00147 #define SR2_SCAN_COMMAND_FAILED 0x4 00148 #define SR2_SCAN_COMMAND_EQUAL 0x8 00149 #define SR2_WRONG_CYLINDER_DETECTED 0x10 /* Mimics SR1_CANNOT_FIND_ID_ADDRESS */ 00150 #define SR2_CRC_ERROR_IN_SECTOR_DATA 0x20 00151 #define SR2_SECTOR_WITH_DELETED_DATA 0x40 00152 00153 /* STATUS_REGISTER_3 */ 00154 #define SR3_UNIT_SELECTED 0x3 /* Covers two bits; defined below */ 00155 #define SR3_SIDE_HEAD_SELECT_STATUS 0x4 /* Values defined below */ 00156 #define SR3_TWO_SIDED_STATUS_SIGNAL 0x8 00157 #define SR3_TRACK_ZERO_STATUS_SIGNAL 0x10 00158 #define SR3_READY_STATUS_SIGNAL 0x20 00159 #define SR3_WRITE_PROTECT_STATUS_SIGNAL 0x40 00160 #define SR3_FAULT_STATUS_SIGNAL 0x80 00161 00162 /* SR3_UNIT_SELECTED */ 00163 #define SR3_UNIT_SELECTED_A 0x0 00164 #define SR3_UNIT_SELECTED_B 0x1 00165 #define SR3_UNIT_SELECTED_C 0x2 00166 #define SR3_UNIT_SELECTED_D 0x3 00167 00168 /* SR3_SIDE_HEAD_SELECT_STATUS */ 00169 #define SR3_SHSS_HEAD_0 0x0 00170 #define SR3_SHSS_HEAD_1 0x1 00171 00172 /* DIGITAL_INPUT_REGISTER */ 00173 #define DIR_HIGH_DENSITY_SELECT 0x1 00174 #define DIR_DISKETTE_CHANGE 0x80 00175 00176 /* CONFIGURATION_CONTROL_REGISTER */ 00177 #define CCR_DRC 0x3 /* Covers two bits, defined below */ 00178 #define CCR_DRC_0 0x1 00179 #define CCR_DRC_1 0x2 00180 00181 /* CCR_DRC */ 00182 #define CCR_DRC_500000 0x0 00183 #define CCR_DRC_250000 0x2 00184 00185 /* Commands */ 00186 #define COMMAND_READ_TRACK 0x2 00187 #define COMMAND_SPECIFY 0x3 00188 #define COMMAND_SENSE_DRIVE_STATUS 0x4 00189 #define COMMAND_WRITE_DATA 0x5 00190 #define COMMAND_READ_DATA 0x6 00191 #define COMMAND_RECALIBRATE 0x7 00192 #define COMMAND_SENSE_INTERRUPT_STATUS 0x8 00193 #define COMMAND_WRITE_DELETED_DATA 0x9 00194 #define COMMAND_READ_ID 0xA 00195 #define COMMAND_READ_DELETED_DATA 0xC 00196 #define COMMAND_FORMAT_TRACK 0xD 00197 #define COMMAND_SEEK 0xF 00198 #define COMMAND_VERSION 0x10 00199 #define COMMAND_SCAN_EQUAL 0x11 00200 #define COMMAND_CONFIGURE 0x13 00201 #define COMMAND_SCAN_LOW_OR_EQUAL 0x19 00202 #define COMMAND_SCAN_HIGH_OR_EQUAL 0x1D 00203 00204 /* COMMAND_READ_DATA constants */ 00205 #define READ_DATA_DS0 0x1 00206 #define READ_DATA_DS1 0x2 00207 #define READ_DATA_HDS 0x4 00208 #define READ_DATA_SK 0x20 00209 #define READ_DATA_MFM 0x40 00210 #define READ_DATA_MT 0x80 00211 00212 /* COMMAND_READ_ID constants */ 00213 #define READ_ID_MFM 0x40 00214 00215 /* COMMAND_SPECIFY constants */ 00216 #define SPECIFY_HLT_1M 0x10 /* 16ms; based on intel data sheet */ 00217 #define SPECIFY_HLT_500K 0x8 /* 16ms; based on intel data sheet */ 00218 #define SPECIFY_HLT_300K 0x6 /* 16ms; based on intel data sheet */ 00219 #define SPECIFY_HLT_250K 0x4 /* 16ms; based on intel data sheet */ 00220 #define SPECIFY_HUT_1M 0x0 /* Need to figure out these eight values; 0 is max */ 00221 #define SPECIFY_HUT_500K 0x0 00222 #define SPECIFY_HUT_300K 0x0 00223 #define SPECIFY_HUT_250K 0x0 00224 #define SPECIFY_SRT_1M 0x0 00225 #define SPECIFY_SRT_500K 0x0 00226 #define SPECIFY_SRT_300K 0x0 00227 #define SPECIFY_SRT_250K 0x0 00228 00229 /* Command byte 1 constants */ 00230 #define COMMAND_UNIT_SELECT 0x3 /* Covers two bits; defined below */ 00231 #define COMMAND_UNIT_SELECT_0 0x1 00232 #define COMMAND_UNIT_SELECT_1 0x2 00233 #define COMMAND_HEAD_NUMBER 0x4 00234 #define COMMAND_HEAD_NUMBER_SHIFT 0x2 00235 00236 /* COMMAND_VERSION */ 00237 #define VERSION_ENHANCED 0x90 00238 00239 /* COMMAND_UNIT_SELECT */ 00240 #define CUS_UNIT_0 0x0 00241 #define CUS_UNIT_1 0x1 00242 00243 /* COMMAND_CONFIGURE constants */ 00244 #define CONFIGURE_FIFOTHR 0xf 00245 #define CONFIGURE_POLL 0x10 00246 #define CONFIGURE_EFIFO 0x20 00247 #define CONFIGURE_EIS 0x40 00248 #define CONFIGURE_PRETRK 0xff 00249 00250 /* Command Head Number Constants */ 00251 #define COMMAND_HEAD_0 0x0 00252 #define COMMAND_HEAD_1 0x1 00253 00254 /* Bytes per sector constants */ 00255 #define HW_128_BYTES_PER_SECTOR 0x0 00256 #define HW_256_BYTES_PER_SECTOR 0x1 00257 #define HW_512_BYTES_PER_SECTOR 0x2 00258 #define HW_1024_BYTES_PER_SECTOR 0x3 00259 00260 /* 00261 * FUNCTIONS 00262 */ 00263 NTSTATUS NTAPI 00264 HwTurnOnMotor(PDRIVE_INFO DriveInfo); 00265 00266 NTSTATUS NTAPI 00267 HwSenseDriveStatus(PDRIVE_INFO DriveInfo); 00268 00269 NTSTATUS NTAPI 00270 HwReadWriteData(PCONTROLLER_INFO ControllerInfo, 00271 BOOLEAN Read, 00272 UCHAR Unit, 00273 UCHAR Cylinder, 00274 UCHAR Head, 00275 UCHAR Sector, 00276 UCHAR BytesPerSector, 00277 UCHAR EndOfTrack, 00278 UCHAR Gap3Length, 00279 UCHAR DataLength); 00280 00281 NTSTATUS NTAPI 00282 HwRecalibrate(PDRIVE_INFO DriveInfo); 00283 00284 NTSTATUS NTAPI 00285 HwSenseInterruptStatus(PCONTROLLER_INFO ControllerInfo); 00286 00287 NTSTATUS NTAPI 00288 HwReadId(PDRIVE_INFO DriveInfo, UCHAR Head); 00289 00290 NTSTATUS NTAPI 00291 HwFormatTrack(PCONTROLLER_INFO ControllerInfo, 00292 UCHAR Unit, 00293 UCHAR Head, 00294 UCHAR BytesPerSector, 00295 UCHAR SectorsPerTrack, 00296 UCHAR Gap3Length, 00297 UCHAR FillerPattern); 00298 00299 NTSTATUS NTAPI 00300 HwSeek(PDRIVE_INFO DriveInfo, UCHAR Cylinder); 00301 00302 NTSTATUS NTAPI 00303 HwReadWriteResult(PCONTROLLER_INFO ControllerInfo); 00304 00305 NTSTATUS NTAPI 00306 HwGetVersion(PCONTROLLER_INFO ControllerInfo); 00307 00308 NTSTATUS NTAPI 00309 HwConfigure(PCONTROLLER_INFO ControllerInfo, 00310 BOOLEAN EIS, 00311 BOOLEAN EFIFO, 00312 BOOLEAN POLL, 00313 UCHAR FIFOTHR, 00314 UCHAR PRETRK) ; 00315 00316 NTSTATUS NTAPI 00317 HwRecalibrateResult(PCONTROLLER_INFO ControllerInfo); 00318 00319 NTSTATUS NTAPI 00320 HwDiskChanged(PDRIVE_INFO DriveInfo, 00321 PBOOLEAN DiskChanged); 00322 00323 NTSTATUS NTAPI 00324 HwSenseDriveStatusResult(PCONTROLLER_INFO ControllerInfo, 00325 PUCHAR Status); 00326 00327 NTSTATUS NTAPI 00328 HwSpecify(PCONTROLLER_INFO ControllerInfo, 00329 UCHAR HeadLoadTime, 00330 UCHAR HeadUnloadTime, 00331 UCHAR StepRateTime, 00332 BOOLEAN NonDma); 00333 00334 NTSTATUS NTAPI 00335 HwReadIdResult(PCONTROLLER_INFO ControllerInfo, 00336 PUCHAR CurCylinder, 00337 PUCHAR CurHead); 00338 00339 NTSTATUS NTAPI 00340 HwSetDataRate(PCONTROLLER_INFO ControllerInfo, UCHAR DataRate); 00341 00342 NTSTATUS NTAPI 00343 HwReset(PCONTROLLER_INFO Controller); 00344 00345 NTSTATUS NTAPI 00346 HwPowerOff(PCONTROLLER_INFO ControllerInfo); 00347 00348 VOID NTAPI 00349 HwDumpRegisters(PCONTROLLER_INFO ControllerInfo); 00350 00351 NTSTATUS NTAPI 00352 HwTurnOffMotor(PCONTROLLER_INFO ControllerInfo); 00353
Generated on Sat May 26 2012 04:17:58 for ReactOS by
1.7.6.1
