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00001 /*++
00002 
00003 Copyright (C) Microsoft Corporation, 1999 - 1999
00004 
00005 Module Name:
00006 
00007     ideuser.h
00008 
00009 Abstract:
00010 
00011     These are the structures and defines that are used in the
00012     PCI IDE mini drivers.
00013 
00014 Revision History:
00015 
00016 --*/
00017 
00018 #if !defined (___ideuser_h___)
00019 #define ___ideuser_h___
00020 
00021   
00022 #define PIO_MODE0           (1 << 0)
00023 #define PIO_MODE1           (1 << 1)
00024 #define PIO_MODE2           (1 << 2)
00025 #define PIO_MODE3           (1 << 3)
00026 #define PIO_MODE4           (1 << 4)
00027 
00028 #define SWDMA_MODE0         (1 << 5)
00029 #define SWDMA_MODE1         (1 << 6)
00030 #define SWDMA_MODE2         (1 << 7)
00031 
00032 #define MWDMA_MODE0         (1 << 8)
00033 #define MWDMA_MODE1         (1 << 9)
00034 #define MWDMA_MODE2         (1 << 10)
00035 
00036 #define UDMA_MODE0          (1 << 11)
00037 #define UDMA_MODE1          (1 << 12)
00038 #define UDMA_MODE2          (1 << 13)
00039 #define UDMA_MODE3          (1 << 14)
00040 #define UDMA_MODE4          (1 << 15)
00041 #define UDMA_MODE5          (1 << 16)
00042 
00043 #define PIO_SUPPORT         (PIO_MODE0      | PIO_MODE1     | PIO_MODE2    | PIO_MODE3     | PIO_MODE4)
00044 #define SWDMA_SUPPORT       (SWDMA_MODE0    | SWDMA_MODE1   | SWDMA_MODE2)
00045 #define MWDMA_SUPPORT       (MWDMA_MODE0    | MWDMA_MODE1   | MWDMA_MODE2)
00046 #define UDMA33_SUPPORT      (UDMA_MODE0     | UDMA_MODE1    | UDMA_MODE2)
00047 #define UDMA66_SUPPORT      (UDMA_MODE3     | UDMA_MODE4)
00048 #define UDMA100_SUPPORT     (UDMA_MODE5 )
00049 #define UDMA_SUPPORT        (UNINITIALIZED_TRANSFER_MODE & (~(PIO_SUPPORT | SWDMA_SUPPORT | MWDMA_SUPPORT)))
00050 
00051 #define DMA_SUPPORT         (SWDMA_SUPPORT  | MWDMA_SUPPORT | UDMA_SUPPORT)
00052 #define ALL_MODE_SUPPORT    (PIO_SUPPORT | DMA_SUPPORT)
00053 
00054 #define PIO0                        0
00055 #define PIO1                        1
00056 #define PIO2                        2
00057 #define PIO3                        3
00058 #define PIO4                        4
00059 #define SWDMA0                      5
00060 #define SWDMA1                      6
00061 #define SWDMA2                      7
00062 #define MWDMA0                      8
00063 #define MWDMA1                      9
00064 #define MWDMA2                      10
00065 #define UDMA0                       11
00066 
00067 #define MAX_XFER_MODE               17
00068 #define UNINITIALIZED_CYCLE_TIME    0xffffffff
00069 #define UNINITIALIZED_TRANSFER_MODE 0x7fffffff
00070 #define IS_DEFAULT(mode)    (!(mode & 0x80000000))
00071 
00072 #define GenTransferModeMask(i, mode) {\
00073     ULONG temp=0xffffffff; \
00074     mode |= (temp >> (31-(i)));\
00075 }
00076 
00077 //
00078 // mode should not be 0
00079 //
00080 #define GetHighestTransferMode(mode, i) {\
00081     ULONG temp=(mode); \
00082     ASSERT(temp); \
00083     i=0; \
00084     while ( temp) { \
00085         temp = (temp >> 1);\
00086         i++;\
00087     } \
00088     i--; \
00089 }
00090 
00091 #define GetHighestDMATransferMode(mode, i) {\
00092     ULONG temp=mode >> 5;\
00093     i=5; \
00094     while ( temp) { \
00095         temp = (temp >> 1); \
00096         i++; \
00097     } \
00098     i--; \
00099 }
00100 #define GetHighestPIOTransferMode(mode, i) { \
00101     ULONG temp = (mode & PIO_SUPPORT); \
00102     i=0; \
00103     temp = temp >> 1; \
00104     while (temp) { \
00105         temp = temp >> 1; \
00106         i++; \
00107     } \
00108 }
00109 
00110 #define SetDefaultTiming(timingTable, length) {\
00111     timingTable[0]=PIO_MODE0_CYCLE_TIME; \
00112     timingTable[1]=PIO_MODE1_CYCLE_TIME; \
00113     timingTable[2]=PIO_MODE2_CYCLE_TIME; \
00114     timingTable[3]=PIO_MODE3_CYCLE_TIME; \
00115     timingTable[4]=PIO_MODE4_CYCLE_TIME; \
00116     timingTable[5]=SWDMA_MODE0_CYCLE_TIME; \
00117     timingTable[6]=SWDMA_MODE1_CYCLE_TIME; \
00118     timingTable[7]=SWDMA_MODE2_CYCLE_TIME; \
00119     timingTable[8]=MWDMA_MODE0_CYCLE_TIME; \
00120     timingTable[9]=MWDMA_MODE1_CYCLE_TIME; \
00121     timingTable[10]=MWDMA_MODE2_CYCLE_TIME; \
00122     timingTable[11]=UDMA_MODE0_CYCLE_TIME; \
00123     timingTable[12]=UDMA_MODE1_CYCLE_TIME; \
00124     timingTable[13]=UDMA_MODE2_CYCLE_TIME; \
00125     timingTable[14]=UDMA_MODE3_CYCLE_TIME; \
00126     timingTable[15]=UDMA_MODE4_CYCLE_TIME; \
00127     timingTable[16]=UDMA_MODE5_CYCLE_TIME; \
00128     length = MAX_XFER_MODE; \
00129 }
00130 
00131 #endif // ___ideuser_h___
00132
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