PCI_AGP_COMMAND PCI_AGP_COMMAND_64BIT PCI_AGP_COMMAND_AGP PCI_AGP_COMMAND_FW PCI_AGP_COMMAND_RATE1 PCI_AGP_COMMAND_RATE2 PCI_AGP_COMMAND_RATE4 PCI_AGP_COMMAND_RQ_MASK PCI_AGP_COMMAND_SBA PCI_AGP_RFU PCI_AGP_SIZEOF PCI_AGP_STATUS PCI_AGP_STATUS_64BIT PCI_AGP_STATUS_FW PCI_AGP_STATUS_RATE1 PCI_AGP_STATUS_RATE2 PCI_AGP_STATUS_RATE4 PCI_AGP_STATUS_RQ_MASK PCI_AGP_STATUS_SBA PCI_AGP_VERSION PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS_IO_MASK PCI_BASE_ADDRESS_MEM_MASK PCI_BASE_ADDRESS_MEM_PREFETCH PCI_BASE_ADDRESS_MEM_TYPE_1M PCI_BASE_ADDRESS_MEM_TYPE_32 PCI_BASE_ADDRESS_MEM_TYPE_64 PCI_BASE_ADDRESS_MEM_TYPE_MASK PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_IO PCI_BASE_ADDRESS_SPACE_MEMORY PCI_BIST PCI_BIST_CAPABLE PCI_BIST_CODE_MASK PCI_BIST_START PCI_BRIDGE_CONTROL PCI_BRIDGE_CTL_BUS_RESET PCI_BRIDGE_CTL_FAST_BACK PCI_BRIDGE_CTL_MASTER_ABORT PCI_BRIDGE_CTL_NO_ISA PCI_BRIDGE_CTL_PARITY PCI_BRIDGE_CTL_SERR PCI_BRIDGE_CTL_VGA PCI_BRIDGE_RESOURCES PCI_CACHE_LINE_SIZE PCI_CAP_FLAGS PCI_CAP_ID_AGP PCI_CAP_ID_CHSWP PCI_CAP_ID_MSI PCI_CAP_ID_PM PCI_CAP_ID_SLOTID PCI_CAP_ID_VPD PCI_CAP_LIST_ID PCI_CAP_LIST_NEXT PCI_CAP_SIZEOF PCI_CAPABILITY_LIST PCI_CARDBUS_CIS PCI_CB_BRIDGE_CONTROL PCI_CB_BRIDGE_CTL_16BIT_INT PCI_CB_BRIDGE_CTL_CB_RESET PCI_CB_BRIDGE_CTL_ISA PCI_CB_BRIDGE_CTL_MASTER_ABORT PCI_CB_BRIDGE_CTL_PARITY PCI_CB_BRIDGE_CTL_POST_WRITES PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 PCI_CB_BRIDGE_CTL_SERR PCI_CB_BRIDGE_CTL_VGA PCI_CB_CAPABILITY_LIST PCI_CB_CARD_BUS PCI_CB_IO_BASE_0 PCI_CB_IO_BASE_0_HI PCI_CB_IO_BASE_1 PCI_CB_IO_BASE_1_HI PCI_CB_IO_LIMIT_0 PCI_CB_IO_LIMIT_0_HI PCI_CB_IO_LIMIT_1 PCI_CB_IO_LIMIT_1_HI PCI_CB_IO_RANGE_MASK PCI_CB_LATENCY_TIMER PCI_CB_LEGACY_MODE_BASE PCI_CB_MEMORY_BASE_0 PCI_CB_MEMORY_BASE_1 PCI_CB_MEMORY_LIMIT_0 PCI_CB_MEMORY_LIMIT_1 PCI_CB_PRIMARY_BUS PCI_CB_SEC_STATUS PCI_CB_SUBORDINATE_BUS PCI_CB_SUBSYSTEM_ID PCI_CB_SUBSYSTEM_VENDOR_ID PCI_CLASS_DEVICE PCI_CLASS_PROG PCI_CLASS_REVISION PCI_COMMAND PCI_COMMAND_FAST_BACK PCI_COMMAND_INVALIDATE PCI_COMMAND_IO PCI_COMMAND_MASTER PCI_COMMAND_MEMORY PCI_COMMAND_PARITY PCI_COMMAND_SERR PCI_COMMAND_SPECIAL PCI_COMMAND_VGA_PALETTE PCI_COMMAND_WAIT PCI_DEVFN PCI_DEVICE_ID PCI_FUNC PCI_HEADER_TYPE PCI_HEADER_TYPE_BRIDGE PCI_HEADER_TYPE_CARDBUS PCI_HEADER_TYPE_NORMAL PCI_INTERRUPT_LINE PCI_INTERRUPT_PIN PCI_IO_BASE PCI_IO_BASE_UPPER16 PCI_IO_LIMIT PCI_IO_LIMIT_UPPER16 PCI_IO_RANGE_MASK PCI_IO_RANGE_TYPE_16 PCI_IO_RANGE_TYPE_32 PCI_IO_RANGE_TYPE_MASK PCI_LATENCY_TIMER PCI_MAX_LAT PCI_MEMORY_BASE PCI_MEMORY_LIMIT PCI_MEMORY_RANGE_MASK PCI_MEMORY_RANGE_TYPE_MASK PCI_MIN_GNT PCI_MSI_ADDRESS_HI PCI_MSI_ADDRESS_LO PCI_MSI_DATA_32 PCI_MSI_DATA_64 PCI_MSI_FLAGS PCI_MSI_FLAGS_64BIT PCI_MSI_FLAGS_ENABLE PCI_MSI_FLAGS_QMASK PCI_MSI_FLAGS_QSIZE PCI_MSI_RFU PCI_NUM_RESOURCES PCI_PM_BPCC_ENABLE PCI_PM_CAP_AUX_POWER PCI_PM_CAP_D1 PCI_PM_CAP_D2 PCI_PM_CAP_DSI PCI_PM_CAP_PME PCI_PM_CAP_PME_CLOCK PCI_PM_CAP_PME_D0 PCI_PM_CAP_PME_D1 PCI_PM_CAP_PME_D2 PCI_PM_CAP_PME_D3 PCI_PM_CAP_PME_D3cold PCI_PM_CAP_PME_MASK PCI_PM_CAP_RESERVED PCI_PM_CAP_VER_MASK PCI_PM_CTRL PCI_PM_CTRL_DATA_SCALE_MASK PCI_PM_CTRL_DATA_SEL_MASK PCI_PM_CTRL_PME_ENABLE PCI_PM_CTRL_PME_STATUS PCI_PM_CTRL_STATE_MASK PCI_PM_DATA_REGISTER PCI_PM_PMC PCI_PM_PPB_B2_B3 PCI_PM_PPB_EXTENSIONS PCI_PM_SIZEOF PCI_PREF_BASE_UPPER32 PCI_PREF_LIMIT_UPPER32 PCI_PREF_MEMORY_BASE PCI_PREF_MEMORY_LIMIT PCI_PREF_RANGE_MASK PCI_PREF_RANGE_TYPE_32 PCI_PREF_RANGE_TYPE_64 PCI_PREF_RANGE_TYPE_MASK PCI_PRIMARY_BUS PCI_REGION_FLAG_MASK PCI_REVISION_ID PCI_ROM_ADDRESS PCI_ROM_ADDRESS1 PCI_ROM_ADDRESS_ENABLE PCI_ROM_ADDRESS_MASK PCI_ROM_RESOURCE PCI_SEC_LATENCY_TIMER PCI_SEC_STATUS PCI_SECONDARY_BUS PCI_SID_CHASSIS_NR PCI_SID_ESR PCI_SID_ESR_FIC PCI_SID_ESR_NSLOTS PCI_SLOT PCI_STATUS PCI_STATUS_66MHZ PCI_STATUS_CAP_LIST PCI_STATUS_DETECTED_PARITY PCI_STATUS_DEVSEL_FAST PCI_STATUS_DEVSEL_MASK PCI_STATUS_DEVSEL_MEDIUM PCI_STATUS_DEVSEL_SLOW PCI_STATUS_FAST_BACK PCI_STATUS_PARITY PCI_STATUS_REC_MASTER_ABORT PCI_STATUS_REC_TARGET_ABORT PCI_STATUS_SIG_SYSTEM_ERROR PCI_STATUS_SIG_TARGET_ABORT PCI_STATUS_UDF PCI_SUBORDINATE_BUS PCI_SUBSYSTEM_ID PCI_SUBSYSTEM_VENDOR_ID PCI_VENDOR_ID

#define PCI_SUBSYSTEM_VENDOR_ID   0x2c Definition at line 99 of file pcidef.h.