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ReactOS Development > Doxygenioaccess.h
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00001 /* 00002 * ioaccess.h 00003 * 00004 * Windows Device Driver Kit 00005 * 00006 * This file is part of the w32api package. 00007 * 00008 * THIS SOFTWARE IS NOT COPYRIGHTED 00009 * 00010 * This source code is offered for use in the public domain. You may 00011 * use, modify or distribute it freely. 00012 * 00013 * This code is distributed in the hope that it will be useful but 00014 * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY 00015 * DISCLAIMED. This includes but is not limited to warranties of 00016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 00017 * 00018 */ 00019 #ifndef __IOACCESS_H 00020 #define __IOACCESS_H 00021 00022 #ifdef __cplusplus 00023 extern "C" { 00024 #endif 00025 00026 #define H2I(p) PtrToUshort(p) 00027 00028 #ifndef NO_PORT_MACROS 00029 00030 #if defined(_X86_) || defined(_M_AMD64) 00031 #define READ_REGISTER_UCHAR(r) (*(volatile UCHAR *)(r)) 00032 #define READ_REGISTER_USHORT(r) (*(volatile USHORT *)(r)) 00033 #define READ_REGISTER_ULONG(r) (*(volatile ULONG *)(r)) 00034 #define WRITE_REGISTER_UCHAR(r, v) (*(volatile UCHAR *)(r) = (v)) 00035 #define WRITE_REGISTER_USHORT(r, v) (*(volatile USHORT *)(r) = (v)) 00036 #define WRITE_REGISTER_ULONG(r, v) (*(volatile ULONG *)(r) = (v)) 00037 #define READ_PORT_UCHAR(p) (UCHAR)(__inbyte (H2I(p))) 00038 #define READ_PORT_USHORT(p) (USHORT)(__inword (H2I(p))) 00039 #define READ_PORT_ULONG(p) (ULONG)(__indword (H2I(p))) 00040 #define WRITE_PORT_UCHAR(p, v) __outbyte (H2I(p), (v)) 00041 #define WRITE_PORT_USHORT(p, v) __outword (H2I(p), (v)) 00042 #define WRITE_PORT_ULONG(p, v) __outdword (H2I(p), (v)) 00043 00044 #define MEMORY_BARRIER() 00045 00046 #elif defined(_PPC_) || defined(_MIPS_) || defined(_ARM_) 00047 00048 #define READ_REGISTER_UCHAR(r) (*(volatile UCHAR * const)(r)) 00049 #define READ_REGISTER_USHORT(r) (*(volatile USHORT * const)(r)) 00050 #define READ_REGISTER_ULONG(r) (*(volatile ULONG * const)(r)) 00051 #define WRITE_REGISTER_UCHAR(r, v) (*(volatile UCHAR * const)(r) = (v)) 00052 #define WRITE_REGISTER_USHORT(r, v) (*(volatile USHORT * const)(r) = (v)) 00053 #define WRITE_REGISTER_ULONG(r, v) (*(volatile ULONG * const)(r) = (v)) 00054 #define READ_PORT_UCHAR(r) READ_REGISTER_UCHAR(r) 00055 #define READ_PORT_USHORT(r) READ_REGISTER_USHORT(r) 00056 #define READ_PORT_ULONG(r) READ_REGISTER_ULONG(r) 00057 #define WRITE_PORT_UCHAR(p, v) WRITE_REGISTER_UCHAR(p, (UCHAR) (v)) 00058 #define WRITE_PORT_USHORT(p, v) WRITE_REGISTER_USHORT(p, (USHORT) (v)) 00059 #define WRITE_PORT_ULONG(p, v) WRITE_REGISTER_ULONG(p, (ULONG) (v)) 00060 00061 #else 00062 00063 #error Unsupported architecture 00064 00065 #endif 00066 00067 #endif /* NO_PORT_MACROS */ 00068 00069 #ifdef __cplusplus 00070 } 00071 #endif 00072 00073 #endif /* __IOACCESS_H */ Generated on Fri May 25 2012 04:28:32 for ReactOS by
1.7.6.1
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