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ReactOS Development > Doxygen

ports.c
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00001 /*
00002  * COPYRIGHT:   See COPYING in the top level directory
00003  * PROJECT:     ReactOS TCP/IP protocol driver
00004  * FILE:        tcpip/ports.c
00005  * PURPOSE:     Port allocation
00006  * PROGRAMMERS: arty (ayerkes@speakeasy.net)
00007  * REVISIONS:
00008  *   arty 20041114 Created
00009  */
00010 
00011 #include "precomp.h"
00012 
00013 NTSTATUS PortsStartup( PPORT_SET PortSet,
00014            UINT StartingPort,
00015            UINT PortsToManage ) {
00016     PortSet->StartingPort = StartingPort;
00017     PortSet->PortsToOversee = PortsToManage;
00018 
00019     PortSet->ProtoBitBuffer =
00020     ExAllocatePoolWithTag( NonPagedPool, (PortSet->PortsToOversee + 7) / 8,
00021                                PORT_SET_TAG );
00022     if(!PortSet->ProtoBitBuffer) return STATUS_INSUFFICIENT_RESOURCES;
00023     RtlInitializeBitMap( &PortSet->ProtoBitmap,
00024              PortSet->ProtoBitBuffer,
00025              PortSet->PortsToOversee );
00026     RtlClearAllBits( &PortSet->ProtoBitmap );
00027     KeInitializeSpinLock( &PortSet->Lock );
00028     return STATUS_SUCCESS;
00029 }
00030 
00031 VOID PortsShutdown( PPORT_SET PortSet ) {
00032     ExFreePoolWithTag( PortSet->ProtoBitBuffer, PORT_SET_TAG );
00033 }
00034 
00035 VOID DeallocatePort( PPORT_SET PortSet, ULONG Port ) {
00036     KIRQL OldIrql;
00037 
00038     Port = htons(Port);
00039     ASSERT(Port >= PortSet->StartingPort);
00040     ASSERT(Port < PortSet->StartingPort + PortSet->PortsToOversee);
00041 
00042     KeAcquireSpinLock( &PortSet->Lock, &OldIrql );
00043     RtlClearBits( &PortSet->ProtoBitmap, Port - PortSet->StartingPort, 1 );
00044     KeReleaseSpinLock( &PortSet->Lock, OldIrql );
00045 }
00046 
00047 BOOLEAN AllocatePort( PPORT_SET PortSet, ULONG Port ) {
00048     BOOLEAN Clear;
00049     KIRQL OldIrql;
00050 
00051     Port = htons(Port);
00052 
00053     if ((Port < PortSet->StartingPort) ||
00054         (Port >= PortSet->StartingPort + PortSet->PortsToOversee))
00055     {
00056        return FALSE;
00057     }
00058 
00059     Port -= PortSet->StartingPort;
00060 
00061     KeAcquireSpinLock( &PortSet->Lock, &OldIrql );
00062     Clear = RtlAreBitsClear( &PortSet->ProtoBitmap, Port, 1 );
00063     if( Clear ) RtlSetBits( &PortSet->ProtoBitmap, Port, 1 );
00064     KeReleaseSpinLock( &PortSet->Lock, OldIrql );
00065 
00066     return Clear;
00067 }
00068 
00069 ULONG AllocateAnyPort( PPORT_SET PortSet ) {
00070     ULONG AllocatedPort;
00071     KIRQL OldIrql;
00072 
00073     KeAcquireSpinLock( &PortSet->Lock, &OldIrql );
00074     AllocatedPort = RtlFindClearBits( &PortSet->ProtoBitmap, 1, 0 );
00075     if( AllocatedPort != (ULONG)-1 ) {
00076     RtlSetBit( &PortSet->ProtoBitmap, AllocatedPort );
00077     AllocatedPort += PortSet->StartingPort;
00078     KeReleaseSpinLock( &PortSet->Lock, OldIrql );
00079     return htons(AllocatedPort);
00080     }
00081     KeReleaseSpinLock( &PortSet->Lock, OldIrql );
00082 
00083     return -1;
00084 }
00085 
00086 ULONG AllocatePortFromRange( PPORT_SET PortSet, ULONG Lowest, ULONG Highest ) {
00087     ULONG AllocatedPort;
00088     KIRQL OldIrql;
00089 
00090     if ((Lowest < PortSet->StartingPort) ||
00091         (Highest >= PortSet->StartingPort + PortSet->PortsToOversee))
00092     {
00093         return -1;
00094     }
00095 
00096     Lowest -= PortSet->StartingPort;
00097     Highest -= PortSet->StartingPort;
00098 
00099     KeAcquireSpinLock( &PortSet->Lock, &OldIrql );
00100     AllocatedPort = RtlFindClearBits( &PortSet->ProtoBitmap, 1, Lowest );
00101     if( AllocatedPort != (ULONG)-1 && AllocatedPort <= Highest) {
00102     RtlSetBit( &PortSet->ProtoBitmap, AllocatedPort );
00103     AllocatedPort += PortSet->StartingPort;
00104     KeReleaseSpinLock( &PortSet->Lock, OldIrql );
00105     return htons(AllocatedPort);
00106     }
00107     KeReleaseSpinLock( &PortSet->Lock, OldIrql );
00108 
00109     return -1;
00110 }

Generated on Wed May 23 2012 04:33:53 for ReactOS by doxygen 1.7.6.1

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